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OPTi ACPI Firestar Clock Source



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Integrated Circuit Systems
MK1491E-14 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MK1491-14
OPTi ACPI Firestar Clock Source
Description
The MK1491-14 is a low cost, low jitter, high
performance clock synthesizer for OPTi’s
Firestar and Firestar+ chipsets for Pentium™
Processor-based mobile computer applications.
Using analog Phase-Locked Loop (PLL)
techniques, the device uses a 14.318 MHz
crystal input to produce multiple output
clocks up to 75 MHz. It provides selectable
Host and PCI local bus clocks as well as
selectable clocks for Super I/O or Universal
Serial Bus (USB). The device has up to seven
Host output clocks.
The chip has three different power down
modes that reduce power on various clocks.
Features
• Packaged in 28 pin, 150 mil wide SSOP
• Provides all critical timing for OPTi ACPI Firestar
and Firestar+
• Early Host clock of 3.5ns
• Separate VDD and skew adjust for Host 5,6, and 7
supports field upgrade to Firestar+ and new 2.5V
processors
• 48MHz USB, 24MHz SIO, and Audio clock support
• Single pin CPU(Host) slowdown to 33.3MHz
• Multiple power down modes
• Low EMI Enable pin reduces EMI radiation (patent
pending)
Block Diagram
VDD
3
GND
4
VDD HOST5-7
HS VDDHOST1-4
FS1:0
Synch./Asynch. PCI
STOP#
SLOW#
Low EMI Enable
PS
SEL0
SEL1
HOST/PCI
Clocks
Fixed
Clock
Host/2
MUX
33M
Output
Buffers
Output
Buffers
Output
Buffers
Output
Buffer
4
HOST1:4
2
HOST 5, 7
EHOST6
5
PCI 1:5
F1
XI
14.31818 MHz
crystal
XO
Crystal
Oscillator
Output
Buffer
Output
Buffer
F2
14.318 MHz
MDS 1491-14 B
1 Revision 061801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126 • (408)295-9800tel • www.icst.com


MK1491E-14 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MK1491-14
OPTi ACPI Firestar Clock Source
Pin Assignment
VDD
X14I
X14O
GND
14.3(HS)
HOST1
HOST2
VDDHOST1-4
HOST3
HOST4
GND
HOST5
EHOST6
VDDHOST5-7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Table #1. F1, F2 Frequency
Select (MHz)
28
27
26
25
STOP#
F1(SEL0)
VDD
F2(PS)
SEL1
0
0
SEL0
0
1
F1
14.318
14.318
24 PCI(FS1) 1
0 24.000
23 GND
1 1 16.934
F2
14.318
48.000
14.318
24.576
Table #2. Host/PCI Frequency Select (MHz)
FS1 FS0 HOST PCI (S/A=0) PCI (S/A=1)
0
0 66.66
33.33*
HOST/2
0 1 60 33.33* HOST/2
1 0 75 33.33* HOST/2
1 1 50 33.33* HOST/2
22 PCIF(LE)
21 PCI(SEL1)
*2 MHz Accuracy
20 VDD
Table #3. Host 5-7 Skew Control
Low EMI for HOST & PCI
19 PCI(S/A)
18 PCI(FS0)
17 GND
16 SLOW#
VDDHOST5-7
2.5V
3.3V
HS
0
1
LE Low EMI
0 OFF
1 ON
15 HOST7
Table #4. Power Down Control (IDD measured at 3.3V)
STOP# SLOW# STATE
HOST
11
ON ON
10
SLOW 33 MHz
0 0 CLK OFF LOW
0 1 PLL/OSC OFF LOW
PCI DESCRIPTION
ON All Clocks On.
ON Host Clock smooth frequency transition to and from 33.33 MHz.
* Asynchronously clamp HOST5, 7 to GND. HOST1-4,6, PCIF, F1, F2, 14.3M, continue to run.
LOW All outputs asynchronously clamped low. PLLs and 14.3 MHz oscillators are off.
*PCI Function Select (PS) set at Power Up. PS=0, PCI=LOW; PS=1, PCI=ON when clock is switched to “CLK OFF” mode.
IDD typ.
50 mA
32 mA
44 mA
1 µA
Pin Descriptions
Pin #
Name
1, 20, 26
VDD
2 X14I
3 X14O
4, 11, 17, 23
GND
5 14.3(HS)
6, 7, 9, 10 HOST 1, 2, 3, 4
8 VDD HOST1-4
12 HOST 5
13 EHOST 6
14 VDD HOST5-7
15 HOST7
16 SLOW#
18 PCI(FS0)
19 PCI(S/A)
21 PCI(SEL1)
22 PCIF(LE)
24 PCI(FS1)
25 F2(PS)
27 F1(SEL0)
28 STOP#
Type Description
P Connect to +3.3V. Must be same voltage on all pins.
I Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
O Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
P Connect to Ground.
I/O 14.318 MHz output. Amplitude matches VDD. Skew input control for Host 5-7.
O Host Output clocks 1, 2, 3 and 4. Amplitude matches VDDHOST1-4
P Connect to VDD supply.
O Host Output clock 5. Amplitude matches VDD HOST5-7 .
O Early Host Output clock 6. Amplitude matches VDD HOST5-7 .
P Connect to 2.5 V or 3.3 V. Host 5-7 skew adjusted with HS input. See Table #3 above.
O Host Output clock 7. Amplitude matches VDD HOST5-7 .
I Controls clock frequency and power downs, as defined in Table #4 above.
I/O PCI Output clock, CPU Frequency Select input, as per Table #2 above. Amplitude = VDD.
I/O PCI Output clock, and Asynchronous PCI Select input, as per Table #2 above.
I/O PCI Output clock, and Frequency Select 1 input, as per Table #1 above.
I/O PCI Output clock that stays enabled when other PCI clocks are low. Low EMI enable input.
I/O PCI output and Frequency Select input. See Table #2 above.
I/O Fixed frequency output and PCI Function Select for "CLK OFF" mode.
I/O Fixed frequency output and frequency SEL0 input per Table #1 above.
I Controls clock frequency and power downs, as defined in Table #4 above.
Key: I = Input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms.
Internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28.
MDS 1491-14 B
2 Revision 061801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126 • (408)295-9800tel • www.icst.com




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OPTi ACPI Firestar Clock Source - Integrated Circuit Systems