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ZL50011 반도체 회로 부품 판매점

Flexible 512 Channel DX



Zarlink Semiconductor 로고
Zarlink Semiconductor
ZL50011 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ZL50011
Flexible 512 Channel DX with on-chip
DPLL
Data Sheet
Features
July 2005
• 512 channel x 512 channel non-blocking switch at
2.048 Mbps, 4.096 Mbps or 8.192 Mbps
operation
• Rate conversion between the ST-BUS inputs and
ST-BUS outputs
• Integrated Digital Phase-Locked Loop (DPLL)
meets Telcordia GR-1244-CORE Stratum 4
specifications
• DPLL provides reference monitor, jitter
attenuation and free run functions
• Per-stream ST-BUS input with data rate selection
of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
• Per-stream ST-BUS output with data rate
selection of 2.048 Mbps, 4.096 Mbps or
8.192 Mbps; the output data rate can be different
than the input data rate
• Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
• Per-stream input channel and input bit delay
programming with fractional bit delay
Ordering Information
ZL50011/QCC 160 Pin LQFP
ZL50011/GDC 144 Ball LBGA
• Per-stream output channel and output bit delay
programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock
outputs
• Per-channel constant throughput delay
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel Pseudo Random Bit Sequence
(PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola non-
multiplexed CPUs
• Connection memory block programming capability
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant input
VDD
VSS
RESET
ODE
STi0-15
FPi
CKi
REF
S/P Converter
Input Timing
Data Memory
Connection Memory
DPLL
OSC
APLL
Microprocessor
Interface
and
Internal
Registers
P/S Converter
Output HiZ Control
Output Timing
Test Port
STo0-15
STOHZ0-15
FPo0
CKo0
FPo1
CKo1
FPo2
CKo2
IC0 - 4
CLKBYPS
ICONN1
Figure 1 - ZL50011 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.


ZL50011 데이터시트, 핀배열, 회로
ZL50011
Data Sheet
Applications
• Small and medium digital switching platforms
• Access Servers
• Time Division Multiplexers
• Computer Telephony Integration
• Digital Loop Carriers
Description
The device has 16 ST-BUS inputs (STi0-15) and 16 ST-BUS outputs (STo0-15). It is a non-blocking digital switch
with 512 64 kbps channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The
ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a
per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mbps,
4.096 Mbps or 8.192 Mbps on a per-stream basis. The device also provides 16 high impedance control outputs
(STOHZ 0-15) to support the use of external high impedance control buffers.
The ZL50011 has features that are programmable on a per-stream or per-channel basis including message mode,
input bit delay, output bit advancement, constant throughput delay and high impedance output control.
The on-chip DPLL meets Telcordia GR-1244-CORE stratum 4 specifications (Stratum 4). It accepts a dedicated
timing reference input at either 8 kHz, 1.544 MHz or 2.048 MHz. Alternatively, the reference can be replaced by an
internal 8 kHz signal derived from the ST-BUS input frame boundary. The DPLL provides reference monitor, jitter
attenuation and free run functions. It can be used as a system’s ST-BUS timing source which is synchronized to the
network. The DPLL can also be bypassed so that the device operates under system timing.
2
Zarlink Semiconductor Inc.




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