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QPRO XQ4000E/EX
QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
02
Product Features
• Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
• Also available under the following Standard Microcircuit
Drawings (SMD)
- XC4005E 5962-97522
- XC4010E 5962-97523
- XC4013E 5962-97524
- XC4025E 5962-97525
- XC4028EX 5962-98509
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
· Synchronous write option
· Dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 60 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000E/EX output
Product Specification
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
• Available Speed Grades:
- XQ4000E -3 for plastic packages only
- -4 for ceramic packages only
- XQ4028EX -4 for all packages
More Information
For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate Arrays product specifica-
tion. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1
QPRO XQ4000E/EX QML High-Reliability FPGAs
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Table 1: XQ4000E/EX Field Programmable Gate Arrays
Device
Max.
Logic
Gates
(No RAM)
Max.
RAM Bits
(No
Logic)
Typical
Gate Range
(Logic and
RAM)(1)
CLB
Matrix
XQ4005E 5,000
6,272 3,000 - 9,000 14 x 14
Number
Total
of
CLBs Flip-Flops
196 616
Max.
Decode
Inputs
per Side
42
Max.
User
I/O
112
XQ4010E 10,000 12,800 7,000 - 20,000 20 x 20 400
1,120
60 160
XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576
1,536
72 192
XQ4025E 25,000
XQ4028EX 28,000
32,768 15,000 - 45,000 32 x 32 1,024
32,768 18,000 - 50,000 32 x 32 1,024
2,560
2,560
96 256
96 256
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Packages
PG156,
CB164
PG191,
CB196,
HQ208
PG223,
CB228,
HQ240
PG299,
CB228
PG299,
CB228,
HQ240,
BG352
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings(1)
Symbol
Description
Units
VCC
VIN
VTS
TSTG
TSOL
TJ
Supply voltage relative to GND
Input voltage relative to GND(2)
Voltage applied to High-Z output(2)
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic package
Plastic package
–0.5 to +7.0
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
–65 to +150
+260
+150
+125
V
V
V
°C
°C
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC excursion above VCC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to –2.0V or overshoot to VCC + 2.0V, provided this over or undershoot lasts less than
10 ns and with the forcing current being limited to 200 mA.
2
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
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