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PDF NX29F010 Data sheet ( Hoja de datos )
| Número de pieza | NX29F010 | |
| Descripción | ULTRA-FAST SECTORED FLASH MEMORY | |
| Fabricantes | NexFlash | |
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NX29F010
1M-BIT (128K x 8-bit)
CMOS, 5.0V Only
ULTRA-FAST SECTORED FLASH MEMORY
JUNE 2000
FEATURES
• Ultra-fast Performance
– 35, 45, 55, 70, and 90 ns max. access times
• Temperature Ranges
– Commercial 0oc-70oc
– Industrial -40oc-85oc
• Single 5V-only Power Supply
– 5V ± 10% for Read, Program, and Erase
• CMOS Low Power Consumption
– 20 mA (typical) active read current
– 30 mA (typical) Program/Erase current
• Compatible with JEDEC-Standard Pinouts
– 32-pin DIP, PLCC, TSOP
• Program/function Compatible with AM29F010
– No system firmware changes
– Uses same PROM programer algorithm
• Flexible sector architecture
– Erase any of eight uniform sectors or full chip erase
– Sector protection/unprotection using PROM
programming equipment
• 100,000 Program/Erase cycles
• Embedded algorithms
– Automatically programs and verifies data at
specified address
– Auto-programs and erases the chip or any
designated sector
• Data/Polling and Toggle Bits
– Detect program or erase cycle completion
DESCRIPTION
The NexFlash NX29F010 is a 1 Megabit (131,072 bytes)
single 5.0V-only Sectored Flash Memory. The NX29F010
provides in-system programming with the standard system
5.0V-only Vcc supply and can be programmed or erased in
standard PROM programmers.
The NX29F010 offers access times of 35, 45, 55, 70, and
90 ns allowing high-speed controller and DSPs' to operate
without wait states. Byte-wide data appears on DQ0-DQ7.
Separate chip enable (CE), write enable (WE), and output
enable (OE) controls eliminates bus contention.
Power consumption is greatly reduced when the system
places the device into the Standby Mode.
The device is offered in 32-pin PLCC, TSOP, and PDIP
packages.
Principles of Operation
Only a single 5.0V power supply is required for both read and
write functions. Program or erase operations do not require
12.0V VPP. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single power supply Flash standard. Commands
are written to the command register using standard micro-
processor write timings. Register contents serve as input to
an internal state machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Executing the Program Command Sequence invokes the
Embedded Program Algorithm, an internal algorithm that
automatically times the program pulse widths and verifies
proper cell margin.
This document contains PRELIMINARY data. NexFlash reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, NexFlash Technologies, Inc..
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
1
1 page  
NX29F010
Standby Mode
In the Standby Mode, current consumption is greatly
reduced, and the outputs are placed in the high impedance
state, independent of the OE input. The system can place
the device in the standby mode when it is not reading or
writing to the device.
The device enters the CMOS standby mode when the CE
pin is held at VCC ± 0.5V. The device enters the TTL standby
mode when CE is held at VIH. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
Output Disable Mode
When the OE = VIH, the output from the device is disabled
and the output pins are placed in the high-impedance state.
Auto-select Mode
The auto-select mode provides access to the manufacturer
and device equivalent codes, as well as sector protection
verification codes, via the DQ7-DQ0 pins. This mode is
primarily intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the auto-select codes
can also be accessed in-system through the command
register.
When using programming equipment, the auto-select mode
requires VID (11.5V to 12.5V) on address pin A9. Address
pins A1 and A0 must be as shown in Auto-select Codes
(High Voltage Method), Table 4. In addition, when verifying
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the corre-
sponding Sector Address Table (Table 3). The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in the Command Definitions
table. This method does not require VID. See "Command
Definitions" for details on using the auto-select mode.
Sector Protection/Unprotection
The hardware sector protection feature disables both pro-
gram and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection procedure requires a high
voltage (VID) on address pin A9 and the control pins. Details
on this method are provided in a supplement. Contact an
NexFlash representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected. NexFlash
offers the option of programming and protecting sectors at
its factory prior to shipping the device. Contact a NexFlash
representative for details.
It is possible to determine whether a sector is protected or
unprotected. See "Auto-select Mode" for details.
Table 4. Auto-select Codes (High Voltage Method)
Description
Manufacturer
Equivalent ID
Device
Equivalent ID
Sector Protection
Verification
CE OE WE A16-A14 A13-A10 A9 A8-A2 A1 A0 DQ7-DQ0
L LH
X
X VID X L L 01 (Hex)
L LH
X
X VID X L H 20 (Hex)
L LH
SA
X
VID X
HL
01H
(protected)
00H
(unprotected)
Note:
1. L = VIL , H = VIH , VID = 11.5 TO 12.5V , SA = ADDRESS SECTOR , X = Don't care.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
5
5 Page 
NX29F010
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final WE pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to
toggle. (The system may use either OE or CE to control the
read cycles.) When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
If a program address falls within a protected sector, DQ6
toggles for approximately 2 µs after the program command
sequence is written, then returns to reading array data.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 8 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram.
Reading Toggle Bit DQ6
Refer to Figure 8 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling.
Typically, a system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on DQ7-DQ0 on the following read cycle.
START
ADDR = VA
READ DQ7-DQ0(1)
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
NEW_DQ6 =
OLD_DQ6?
NO
YES
NO
DQ5 = 1?
YES
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
NEW_DQ6 =
OLD_DQ6?
NO
FAIL
YES
PASS
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to '1'. See text.
3. VA = Valid Address.
Figure 8. Toggle Bit Algorithm
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
11
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