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PDF NX25P10 Data sheet ( Hoja de datos )
| Número de pieza | NX25P10 | |
| Descripción | (NX25P10 - NX25P40) 1M BIT 2M BIT AND 4M BIT SERIAL FLASH MEMORY | |
| Fabricantes | NexFlash | |
| Logotipo |  |
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PRELIMINARY
APRIL 2005
1M-BIT, 2M-BIT AND 4M-BIT
Serial Flash Memory with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1
1 page  
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
WP
HOLD
CLK
CS
DI
DO
Write Control
Logic
Status
Register
SPI
Comand and
Control Logic
High-voltage
Generators
Page Address
Latch / Counter
Data
Byte Address
Latch / Counter
Serial Flash Memory Array
07FF00h
070000h
Sector 7
07FFFFh
0700FFh
06FF00h
060000h
Sector 6
06FFFFh
0600FFh
05FF00h
050000h
Sector 5
05FFFFh
0500FFh
04FF00h
040000h
Sector 4
04FFFFh
0400FFh
03FF00h
030000h
Sector 3
03FFFFh
0300FFh
02FF00h
020000h
Sector 2
02FFFFh
0200FFh
01FF00h
010000h
Sector 1
01FFFFh
0100FFh
00FF00h
000000h
Sector 0*
00FFFFh
0000FFh
Begining
Page Address
Ending
Page Address
Column Decode
and 256 Byte Page Buffer
1
2
3
4
5
6
7
8
9
10
11
* Every Sector Consists of 256 Pages of 256 Bytes Each
Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram
12
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
5
5 Page 
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write
Enable Latch (WEL) bit in the Status Register to a 1. The
WEL bit must be set prior to every Page Program, Sector
Erase, Bulk Erase and Write Status Register instruction.
The Write Enable instruction is entered by driving CS low,
1shifting the instruction code “06h” into the Data Input (DI) pin
on the rising edge of CLK, and then driving CS high.
CS
Mode 3
CLK Mode 0
DI
DO
01 2 3 456 7
Instruction (06h)
High Impedance
Figure 4. Write Enable Instruction Sequence Diagram
2
3
4
5
6
Write Disable (04h)
The Write Disable instruction (Figure 5) resets the Write
Enable Latch (WEL) bit in the Status Register to a 0. The
Write Disable instruction is entered by driving CS low,
shifting the instruction code “04h” into the DI pin and then
7
8driving CS high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, and Bulk Erase
instructions.
9
CS
Mode 3
CLK Mode 0
DI
DO
01 2 3 456 7
Instruction (04h)
High Impedance
Figure 5. Write Disable Instruction Sequence Diagram
10
11
12
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NX25P10.PDF ] | |
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