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S71WS512N 반도체 회로 부품 판매점

Migrating from the S71WS512N to the S71WS512P



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S71WS512N 데이터시트, 핀배열, 회로
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S71WS512N to S71WS512P
Migrating from the S71WS512N to the S71WS512P
Application Note
by Daisuke Nakata
1. Introduction
Migrating from the S71WS512N to the monolithic S71WS512P is a simple process; however, the user should be aware of a few
differences between these two parts. These differences are the result of the S71WS512N using two S29WS256N die in series
while the S71WS512P uses a single S29WS512P configuration. This application note describes these differences in detail so
users currently using the S71WS512N configuration can plan ahead and include the necessary software to ensure a smooth
migration to the S71WS512P. Both software and hardware considerations are covered. Table 1.1 shows a comparison of the
key features between the two flash device cores.
Table 1.1 Comparison of Key Features
Futures
Technology
Process Rule
VCC
VIO (VCCQ)
Max Density
Configuration Register
Sector Architecture
Bank Architecture
Bank Size
Boot Option
Common Flash Interface (CFI)
Simultaneous Read/Write
Asynchronous Read Mode
Page Mode Read
Page Size
Synchronous (Burst) Read Mode
Burst Frequency
Burst Length
Single Word / Write Buffer Program
Write Buffer Size
Program Suspend / Program Resume
Sector Erase / Chip Erase
Erase Suspend / Erase Resume
Unlock Bypass / Fast Mode
Accelerated Program / Chip Erase
Sector Protection
Secured Silicon Area
S29WS256N
MirrorBit
110 nm
1.70 V to 1.95 V
=VCC
256 Mb
CR0-CR15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
2 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
4-words
Yes
54 MHz / 66 MHz / 80 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
S29WS512P
MirrorBit
90 nm
1.70 V to 1.95 V
=VCC
512 Mb
CR0.0 - CR0.15, CR1.0 - CR1.15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
4 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
8-words
Yes
54 MHz / 66 MHz / 80 MHz / 108 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
Publication Number 2xWS-N_to_WS-P_AN
Revision 01E
Issue Date October 3, 2006


S71WS512N 데이터시트, 핀배열, 회로
Application Note
2. Performance Characteristics
The 90 nm MirrorBittechnology, on which the S29WS512P is based, allows performance improvements
over the S29WS256N, which is based on 110 nm MirrorBit technology. Table 2.1 shows the performance
comparison between the two devices.
Table 2.1 Performance Comparison
Access Time
Read Access Time
VCC=1.70 V to 1.95 V
CL=30pF
Single Word Programming Time
Max. Async. Access (tACC)
Max. Async. Page Access (tPACC)
Max. Sync. Burst Access (tBACC)
Typ
Max (See Note)
Total 32-Words Buffer Programming Time
Typ
Max (See Note)
Effective Word Programming Time
Typ
Max (See Note)
Sector Erase Time
Typ
Max (See Note)
S29WS256N
80 ns
20 ns
9 ns
40 µs
400 µs
300 µs
3000 µs
9.4 µs
94 µs
150 ms: 16 K-words
600 ms: 64 K-words
2000 ms: 16 K-words
3500 ms: 64 K-words
S29WS512P
80 ns
20 ns
7 ns
30 µs
150 µs
192 µs
960 µs
6 µs
30 µs
150 ms: 16 K-words
600 ms: 64 K-words
1750 ms: 16 K-words
3000 ms: 64 K-words
Note:
Under worst case conditions of 90°C. VCC = 1.70 V. 100,000 cycles.
3. Electrical Specification Changes
I/O Descriptions - Package and Pin Layout
There are also a few hardware changes required for the migration. Since the entire S29WS512P is
addressed with a single chip select, address line A24 has to be connected. Note that some systems may
require a pull down resistor on A24. The two block diagrams in Figure 3.1 illustrate these changes.
F-VCC
Flash-only Address
Shared Address
CLK
WP#
ACC
F1-CE#
OE#
WE#
F-RST#
AVD#
F2-CE#
R-VCC
R-CE1#
R-UB#
R-LB#
R-CE2
R-CRE
Figure 3.1 Block Diagrams
22 VCC VID
DQ15 to DQ0
16
CLK
WP#
ACC
CE#
OE#
Flash 1
Flash 2
WE#
RESET#
AVD#
RDY
22
VCC
VCCQ
CLK I/O15 to I/O0
CE#
WE# pSRAM
OE#
UB#
LB#
WAIT#
VSSQ
AVD#
CRE#
16
DQ15 to DQ0
RDY
VSS
A0-A22
A23
A24 (Note)
CLK
AVD#
F-CE#
F-OE#
F-RST#
F-ACC
F-WP#
F-WE#
R-CE#
R-OE#
R-LB#
R-UB#
R-WE#
R-CRE
S71WS-N
Note:
Pull down resistor may be required for some systems.
A0-A22
A23
A24 (Note)
CLK
AVD#
CE#
OE#
RESET#
ACC
WP#
WE#
WS512P
Flash
Memory
DQ0-DQ15
RDY
VSS
VCC
VCCQ
A0-A22
CLK
AVD#
CE#
OE#
LB#
UB#
WE#
CRE
DQ0-DQ15
128Mb
CellularRAM
Memory
WAIT#
VSS
VCC
VCCQ
S71WS-P
DQ0-DQ15
RDY/WAIT
VSS
F-VCC
VCCQ
R-VCC
2
S71WS512N to S71WS512P
2xWS-N_to_WS-P_AN_01E October 3, 2006




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