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PDF W532 Data sheet ( Hoja de datos )
| Número de pieza | W532 | |
| Descripción | Peak Reducing EMI Solution | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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W532
Features
Frequency Multiplying, Peak Reducing EMI Solution
Table 1. Output Frequency Range Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable frequency range and multiplication factor
• Single 1.25% or 5% center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 16-pin SOIC
Key Specifications
Supply Voltages: ........................................VDD = 3.3V ±0.3V
or VDD = 5V ±10%
Frequency Range: .........................15 MHz ≤ Fout ≤ 120 MHz
Cycle to Cycle Jitter: ......................................... 150 ps (typ.)
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time ................................... 5 ns (max.)
OR2
0
0
1
1
OR1
0
1
0
1
Output Range
(Multiplication Factor Selection)
reserved
15 MHz ≤ FIN ≤ 30 MHz
30 MHz ≤ FIN ≤ 60 MHz
60 MHz ≤ FIN ≤ 120 MHz
Table 2. Modulation Width Selection
MW Output
0 Favg + 0.625% ≥ Fout ≥ Favg – 0.625%
1 Favg + 2.5% ≥ Fout ≥ Favg – 2.5%
Table 3. Input Frequency Range Selection
IR2 IR1
00
01
10
11
Input Range
reserved
15 MHz ≤ FIN ≤ 30 MHz
30 MHz ≤ FIN ≤ 60 MHz
60 MHz ≤ FIN ≤ 120 MHz
Simplified Block Diagram
3.3V or 5.0V
XTAL
Input
X1
X2
W532
Spread Spectrum
Output
(EMI suppressed)
3.3V or 5.0V
Pin Configuration
SOIC
X1
X2
AVDD
*OR1
NC
AGND
^OR2
*SSON#
1
2
3
4
5
6
7
8
16 VDD
15 GND
14 IR1^
13 IR2^
12 SSOUT
11 GND
10 VDD
9 MW*
Oscillator or
Reference Input
X1
W532
Spread Spectrum
Output
(EMI suppressed)
Notes:
1. ^ pins have internal pull-up
2. * pins have internal pull-down
PREMIS is a trademark of Cypress Semiconductor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07253 Rev. *A
Revised December 28, 2002
1 page  
W532
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
Unit
VDD, VIN
TSTG
TA
Voltage on any Pin with Respect to GND
Storage Temperature
Operating Temperature
–0.5 to +7.0
–65 to +150
0 to +70 or
–40 to +85
V
°C
°C
TB Ambient Temperature under Bias
PD Power Dissipation
–55 to +125
0.5
°C
W
DC Electrical Characteristics: 0°C < TA < 70°C or –40°C to +85°C, VDD = 3.3V ±0.3V
Parameter
Description
Test Condition
Min.
IDD Supply Current
tON Power-Up Time
First locked clock cycle after Power
Good
VIL Input Low Voltage
VIH Input High Voltage
2.4
VOL Output Low Voltage
VOH Output High Voltage
2.4
IIL
Input Low Current
Note 4
–50
IIH
Input High Current
Note 4
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
IOH
Output High Current
@ 2.4V, VDD = 3.3V
CI Input Capacitance
RP Input Pull-Up Resistor
ZOUT
Clock Output Impedance
Note:
3. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. Inputs OR2 and IR1:2 have a pull-up resistor, Inputs SSON# OR1 and MW have a pull-down resistor.
Typ.
18
15
15
150
25
Max.
32
5
0.8
0.4
50
7
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
kΩ
Ω
Document #: 38-07253 Rev. *A
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet W532.PDF ] | |
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