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PDF ISL1209 Data sheet ( Hoja de datos )
| Número de pieza | ISL1209 | |
| Descripción | Low Power RTC | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ISL1209
® Real Time Clock/Calendar with Event Detection
Data Sheet
September 27, 2005
FN6109.1
Low Power RTC with Battery Backed
SRAM and Event Detection
The ISL1209 device is a low power real time clock with
Event Detect function, timing and crystal compensation,
clock/calendar, power fail indicator, periodic or polled alarm,
intelligent battery backup switching and battery-backed user
SRAM.
NOTE: The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for hours,
minutes, and seconds. The device has calendar registers for date,
month, year and day of the week. The calendar is accurate through
2099, with automatic leap year correction.
Ordering Information
PART
VDD
RANGE
PART NUMBER MARKING (V)
TEMP
RANGE
(°C)
PACKAGE
ISL1209IU10* AGT
2.7 to 5.5 -40 to 85 10 Ld MSOP
ISL1209IU10Z* ANV
(See Note)
2.7 to 5.5 -40 to 85 10 Ld MSOP
(Pb-free)
*Add “-TK” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
ISL1209
(10 LD MSOP)
TOP VIEW
X1 1
X2 2
VBAT
3
GND
EVIN
4
5
10 VDD
9 IRQ/FOUT
8 SCL
7 SDA
6 EVDET
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• Security and Event Functions
- Tamper detection with Time Stamp
- Event Detection During Battery Packed or Normal
Modes
- Selectable Event Input Sampling Rates Allows Low
Power Operation
- Selectable Glitch Filter on Event Input Monitor
• 15 Selectable Frequency Outputs
• Single Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
• Power Failure Detection
• On-Chip Oscillator Compensation
• 2 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• 400nA Battery Supply Current
• Small Package
- 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Set Top Box/Modem
• POS Equipment
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Test Meters/Fixtures
• Vending Machine Management
• Security and Anti Tampering Applications
- Panel/Enclosure Status
- Warranty Reporting
- Time Stamping Applications
- Patrol/Security Check (Fire or Light Equipment)
- Automotive Applications
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL1209
SDA vs. SCL Timing
tF
tHIGH
SCL
tSU:STA
SDA
(INPUT TIMING)
tSU:DAT
tHD:STA
SDA
(OUTPUT TIMING)
tLOW
tR
tHD:DAT
tAA tDH
Symbol Table
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
N/A
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
Center Line is
High Impedance
tSU:STO
tBUF
5 FN6109.1
September 27, 2005
5 Page 
ISL1209
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1209 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (See
ATR description.)
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (See DTR
description.)
Also provided is the ability to adjust the crystal capacitance
when the ISL1209 switches from VDD to battery backup
mode. (See Battery Mode ATR Selection for more details.)
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:13h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 4 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (2 bytes): Address 12h to 13h.
There are no addresses above 13h.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
11 FN6109.1
September 27, 2005
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ISL1209.PDF ] | |
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