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CRYSTAL CLOCK OSCILLATORS
LVDS UHF CLOCK (XO)
SD-A2D5XXX Series
Data Sheet 0629C
Rev. -
Description
The SD-A2D5XXX Series of quartz crystal oscillators provides ultra high frequency with LVDS
complementary outputs. The outputs can be Tri-stated for test automation or combining multiple clocks. The
device is based on low noise analog harmonic multiplication for higher frequencies, and packaged in a
miniature, low profile leadless ceramic SMD package with 6 gold plated pads.
Applications and Features
• Wide frequency range – 38.0MHz to 800.000MHz
• Fiber Channel; 10 GbE; Infiniband; Network Processors; SOHO Routing
• High Reliability - NEL HALT/HASS qualified for crystal oscillator start-up conditions
• Low Phase Noise, Low Jitter
• High shock resistance, to 1000g
• Ultra High Frequency
• Tight frequency stability - ±20 ppm overall available
• Grounded lid and internal by-pass capacitor reduce EMI
• RoHS Compliant, Lead Free Construction
Creating a Part Number
SD - A 2D5 X X X - FREQ
Package Code
Overall Frequency Stability, ppm
SD 6 pad 5x7mm SMD
E ±20
F ±25
Input Voltage
G ±50
A 3.3V±5%
H ±100
9 Customer specific
Enable Option
H Enable High
L Enable Low
Temperature Range, °C
A 0 to 50
B 0 to 70
C -20 to 70
D -40 to 85
9 Customer specific
357 Beloit Street, P.O. Box 457, Burlington, WI 53105-0457 U.S.A. Phone 262/763-3591 FAX 262/763-2881
CRYSTAL CLOCK OSCILLATORS
SD-A2D5XXX Series Continued
LVDS UHF CLOCK (XO)
Absolute Maximum Ratings
Parameter
Symbol
Value
Operating Temperature Range
To
-40 to +85
Storage Temperature Range
Tst
-50 to +90
Supply Voltage
Vcc -0.5 to 4.5
Enable/Disable Voltage
Ven/dis
0 to Vcc
Electrical Parameters
Parameter
Nominal Frequency
Symb
Fo
Conditions, Note
MIN
38
TYP
Supply Voltage
Vcc Code A
3.135
3.3
Data Sheet 0629C
Rev. -
Unit
ºC
ºC
V
V
MAX
800
3.465
Unit
MHz
V
Supply current
Output Logic Type
Load
Icc
Output Levels
Vod
Vof
Duty Cycle (Symmetry)
Rise/Fall Time
Jitter Integrated
Tr/Tf
J
Wavecrest
characterized
Subharmonics
Phase Noise
£(∆f)
Frequency Stability
∆F/F
Enable High Option
Pin 2 Enabled
Pin 2 Disabled
Enable Low Option
Pin 2 Disabled
Pin 2 Enabled
At receiving end between
the outputs
Differential amplitude
Amplitude error
Offset Voltage
Offset Voltage error
At outputs crossing, room
temperature
20 to 80, 80 to 20 %
Integrated from Phase
Noise, 12 KHz to 20 MHz
, RMS
Random
<320 M
period,
>320 M
Accumul.,
<320 M
pk-to-pk
>320 M
Deterministic <320 M
>320 M
<320 M
>320 M
212.5 MHz @ 10 Hz
@100 Hz
@1 KHz
@10KHz
@100KHz
@>1MHz
Overall, including initial
calibration, temperature,
aging 10 years, shock and
vibration
90
247
1.125
45/55
80
LVDS
100
330
1.25
50/50
0.5
0.3
100
110
454
50
1.375
50
55/45
0.7
2.5
2.5
30
43
6
18
-50
-35
-65
-95
-125
-140
-145
-148
See “Creating a Part Number”
Not all combinations
available, consult factory
mA
Ohm
mV
mV
V
mV
%
ns
ps
ps
ps
ps
dBc
dBc/Hz
ppm
CMOS logic 1 or N/C
CMOS logic 0
0.7 Vcc
0
Vcc
0.3 Vcc
V
CMOS logic 1 or N/C
CMOS logic 0
0.7 Vcc
0
Vcc
0.3 Vcc
V
357 Beloit Street, P.O. Box 457, Burlington, WI 53105-0457 U.S.A. Phone 262/763-3591 FAX 262/763-2881
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