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PDF SC-605 Data sheet ( Hoja de datos )
| Número de pieza | SC-605 | |
| Descripción | Speech And Music Processor | |
| Fabricantes | Sensory | |
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SC-605
Speech And Music Processor
Data sheet
Features
Advanced, integrated speech synthesizer for
high-quality sound.
Operates up to 12.32 MHz (performs up to 12
MIPS).
Single chip solution for up to 37 minutes of
speech (using 2.36 Mb of onboard program
plus data ROM).
Supports high-quality synthesis algorithms
Such as: MX, CX, Simple CX, LX, ADPCM, and
Polyphonic Music.
Simultaneous speech plus music capabilities.
Very low-power operation, ideal for hand-held
devices.
Low-voltage operation, sustainable by three
batteries.
Reduced power stand-by modes, less than 10
µA in Deep-Sleep mode.
640-word RAM.
32 I/O pins consisting of: 24 general-purpose bit
configurable I/O, 8 inputs with programmable
pullup resistors and a dedicated interrupt (key-
scan).
Direct speaker driver, 32 Ω (PDM).
One-bit comparator with edge-detection
interrupt service.
Resistor-trimmed oscillator or 32.768 kHz
crystal reference oscillator.
Serial scan port for in-circuit emulation and
diagnostics.
The SC-605 is sold in die form or 100-pin LQFP
package.
An emulator device is available in a ceramic
package for development (SC-614-P).
Description
The SC-605 is a low-cost, mixed-signal
processor that combines a speech synthesizer,
general-purpose I/O, onboard ROM, and direct
speaker drive in a single package. The
computational unit utilizes a powerful new DSP
which gives the SC-605 unprecedented speed
and computational flexibility compared with
previous devices of its type. The SC-605
supports a variety of speech and audio coding
algorithms, providing a range of options with
respect to speech duration and sound quality.
16-Bit
Microprocessor
640-words
RAM
288 KBytes
ROM
SC-605 Block Diagram
10-Bit
DAC
TIMER 1
TIMER 2
COMPARATOR
PLLM
32 I/O
The device consists of a micro-DSP core,
embedded program, and data memory, and a self-contained clock generation system. General-purpose
periphery is comprised of 32 bits of partially configurable I/O. The core processor is a general-purpose 16-bit
microcontroller with DSP capability. The basic core block includes computational unit (CU), data address unit,
program address unit, two timers, eight level interrupt processor, and several system and control registers. The
core processor gives the SC-605 break-point capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data
memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party
pirating. It is configured in 32K 17-bit words.
The total ROM space is divided into three areas:
1) The lower 2K words are reserved by Sensory, Inc. for the purposes of a built-in self-test
2) The upper 30K words are for user program/data
3) Additional 1.83 Mb data ROM provides data for up to 37 minutes of speech.
© 2002 Sensory Inc.
P/N 80-0209-A
1
1 page  
Data Sheet
SC-605
DC Electrical Characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP§ MAX UNIT
Positive going threshold
2.4
VDD = 3 V
Negative going threshold
1.8 V
RESET_ Threshold changes
Hysteresis
Positive going threshold
0.6
3.3
VDD = 5.2 V Negative going threshold
2.9 V
Hysteresis
0.4
VIH
VIL
IOH¶
IOL¶
IOH (DAC)
IOL (DAC)
Ilkg
VDD = 3 V
High-level input voltage
VDD = 4.5 V
VDD = 5.2 V
VDD = 3 V
Low-level input voltage
VDD = 4.5 V
VDD = 5.2 V
High-level output current per pin of I/O port
VOH = 4 V
Low-level output current per pin of I/O port
High-level output DAC current
VDD = 4.5 V
VOL = 0.5 V
VOH = 4 V
Low-level output DAC current
VOL = 0.5 V
Input leakage current
Excludes OSCIN
23
3 4.5 V
3.5 5.2
01
0 1.5 V
0 1.7
–2 mA
5 mA
–10 mA
20 mA
1 µA
I(STANDBY) Standby current
IDD† Operating current
I(SLEEP-deep)
I(SLEEP-mid) Supply current
I(SLEEP-light)
VIO Input offset voltage
R(PULLUP) F port pullup resistance
RESET is low
0.05 10 µA
VDD = 4.5 V, FCLOCK = 12.32 MHz
15 mA
VDD = 4.5 V, DAC off, ARM set, OSC disabled
0.05 10
VDD = 4.5 V, DAC off, ARM set, OSC enabled
40 60 µA
VDD = 4.5 V, DAC off, ARM clear, OSC enabled
60 100
VDD = 4.5 V, Vref = 1 to 4.25 V
25 50 mV
VDD = 5 V
70 150
KΩ
∆f(RTO-trim) Trim deviation
RRTO = 470 kΩ, VDD = 4.5 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1% ±3%
∆f(RTO-volt) Voltage deviation
RRTO = 470 kΩ, VDD = 3.5 to 5.2 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1.5%
∆f(RTO-temp) Temperature deviation
RRTO = 470 kΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±0.03
%/°C
∆f(RTO-res) Resistance deviation
VDD = 4.5 V, TA = 25°C, R(OSC) = 470 kΩ at ±1%,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1%
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25°C
¶ Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.
External Component Absolute Values
PARAMETER
R(RTO)
C(PLL)
RTO external resistance
PLL external capacitance
TEST CONDITIONS
TA = 25°C, 1% tolerance
TA = 25°C, 10% tolerance
MIN MAX UNIT
470 k
3300
pF
© 2002 Sensory Inc.
P/N 80-0209-A
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SC-605.PDF ] | |
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