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ADV7320 반도체 회로 부품 판매점

(ADV7320 / ADV7321) Multiformat 216 MHz Video Encoder



Analog Devices 로고
Analog Devices
ADV7320 데이터시트, 핀배열, 회로
Multiformat 216 MHz
Video Encoder with Six NSV® 12-Bit DACs
ADV7320/ADV7321
FEATURES
High definition (HD) input formats
16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb
Fully compliant with
SMPTE 274M (1080i, 1080p @ 74.25 MHz)
SMPTE 296M (720p)
SMPTE 240M (1035i)
RGB in 3-bit × 10-bit 4:4:4 input format
HDTV RGB supported
RGB, RGBHV
Other HD formats using async timing mode
Enhanced definition (ED) input formats
8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
RGB in 3-bit × 10-bit 4:4:4 input format
Standard definition (SD) input formats
CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input
HD output formats
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
ED output formats
Macrovision® Rev 1.2 (525p/625p) (ADV7320 only)
CGMS-A (525p/625p)
YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2)
RGB, RGBHV
SD output formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC-compatible composite video
ITU-R BT.470 PAL-compatible composite video
S-video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1 (ADV7320 only)
CGMS/WSS
Closed captioning
GENERAL FEATURES
Simultaneous SD/HD or PS/SD inputs and outputs
Oversampling up to 216 MHz
Programmable DAC gain control
Sync outputs in all modes
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
On-board voltage reference
Six 12-bit NSV (noise shaped video) precision video DACs
2-wire serial I2C® interface, open-drain configuration
Dual I/O supply 2.5 V/3.3 V operation
Analog and digital supply 2.5 V
On-board PLL
64-lead LQFP package
Lead (Pb) free product
APPLICATIONS
EVD (enhanced versatile disk) players
High-end SD/PS DVD recorders/players
SD/PS/HDTV display devices
SD/HDTV set top boxes
Professional video systems
FUNCTIONAL BLOCK DIAGRAM
Y9–Y0
C9–C0
S9–S0
HSYNC
VSYNC
BLANK
CLKIN_A
CLKIN_B
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE
FILTERS
SD TEST PATTERN
D
E PROGRAMMABLE
M RGB MATRIX
U
X
TIMING
GENERATOR
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7320/
ADV7321
12-BIT
DAC
O 12-BIT
V DAC
E
R
S
A
12-BIT
DAC
M
P 12-BIT
L DAC
I
N 12-BIT
G DAC
12-BIT
DAC
I2C
INTERFACE
Figure 1.
GENERAL DESCRIPTION
The ADV®7320/ADV7321 are high speed, digital-to-analog
encoders on single monolithic chips. They include six high
speed NSV video DACs with TTL-compatible inputs. They have
separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept
data in high definition (HD) and/or standard definition (SD)
video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and, therefore, the output signal.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.


ADV7320 데이터시트, 핀배열, 회로
ADV7320/ADV7321
TABLE OF CONTENTS
Features .............................................................................................. 1
General Features ............................................................................... 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Detailed Features .............................................................................. 4
Terminology ...................................................................................... 5
Specifications..................................................................................... 6
Dynamic Specifications ............................................................... 7
Timing Specifications .................................................................. 8
Timing Diagrams.......................................................................... 9
Absolute Maximum Ratings.......................................................... 16
Thermal Characteristics ............................................................ 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 19
MPU Port Description................................................................... 23
Register Access................................................................................ 25
Register Programming............................................................... 25
Subaddress Register (SR7 to SR0) ............................................ 25
Input Configuration ....................................................................... 38
SD Only........................................................................................ 38
PS Only or HDTV Only ............................................................ 38
Simultaneous SD/PS or SD/HDTV.......................................... 38
PS at 27 MHz (Dual Edge) or 54 MHz .................................... 39
Features ............................................................................................ 41
Output Configuration................................................................ 41
HD Async Timing Mode........................................................... 42
HD Timing Reset........................................................................ 43
SD Real-Time Control, Subcarrier Reset, and Timing Reset ....43
Reset Sequence ........................................................................... 45
SD VCR FF/RW Sync ................................................................ 45
Vertical Blanking Interval ......................................................... 46
Subcarrier Frequency Registers................................................ 46
Square Pixel Timing Mode........................................................ 47
Filters............................................................................................ 48
Color Controls and RGB Matrix .............................................. 49
Programmable DAC Gain Control .......................................... 53
Gamma Correction .................................................................... 53
HD Sharpness Filter and Adaptive Filter Controls................ 55
HD Sharpness Filter and
Adaptive Filter Application Examples ..................................... 56
SD Digital Noise Reduction...................................................... 57
Coring Gain Border ................................................................... 58
Coring Gain Data ....................................................................... 58
DNR Threshold .......................................................................... 58
Border Area................................................................................. 58
Block Size Control...................................................................... 58
DNR Input Select Control......................................................... 58
DNR Mode Control ................................................................... 59
Block Offset Control .................................................................. 59
SD Active Video Edge................................................................ 59
SAV/EAV Step-Edge Control ................................................... 59
HSYNC/VSYNC Output Control ............................................ 61
Board Design and Layout.............................................................. 62
DAC Termination and Layout Considerations ...................... 62
Video Output Buffer and Optional Output Filter.................. 62
PCB Board Layout...................................................................... 63
Appendix 1—Copy Generation Management System .............. 65
PS CGMS..................................................................................... 65
HD CGMS................................................................................... 65
SD CGMS .................................................................................... 65
Rev. A | Page 2 of 88




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