T224162B 반도체 회로 부품 판매점
256K x 16 DYNAMIC RAM EDO PAGE MODE
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 Taiwan Memory Technology |
www.DataSheet4U.com
tm TE
CH
DRAM
T224162B
256K x 16 DYNAMIC
RAM
EDO PAGE MODE
FEATURES
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 512-cycle refresh in 8ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• Extended data-out (EDO) PAGE MODE
access cycle.
• BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING
22n s
25ns
28n s
35ns
45n s
50ns
PACKAGE
SOJ
TSOP(II)
EDO
125 MHz
100 MHz
100 MHz
83 MHz
60 MHz
50 MHz
MARKING
J
S
MARKING
-22
-25
-28
-35
-45
-50
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode with Extended
Data Output.
The T224162B CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE. CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
Vcc 1
I/01 2
I/02 3
I/03 4
I/04 5
Vcc 6
I/05 7
I/06 8
I/07 9
I/08 10
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
11
12
13
14
15
16
17
18
19
20
TSOP(II)
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SOJ
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: AUG. 2000
Revision:L
DataSheet4 U .com
www.DataSheet4U.com
tm TE
CH
FUNCTIONAL BLOCK DIAGRAM
T224162B
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
WE
CASL
CASH
CAS
NO.2 CLOCK
GENERATOR
COLUMN.
9 ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
9
ROW.
9 ADDRESS
BUFFERS(9)
NO.1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
9
COLUMN
DECODER
512
8
8
SENSE AMPLIFIERS
VO GATING
512 x 16
DATA-OUT
BUFFER
16
DQ01
.
16 .
DQ16
OE
512 x 512 x 16
9 512 MEMORY
ARRAY
Vcc
Vss
PIN DESCRIPTIONS
PIN NO.
16~19,22~26
14
28
29
13
27
2~5,6~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
SYM.
A0-A8
RAS
CASH
CASL
WE
OE
I/O1 - I/O16
Vcc
Vss
NC
TYPE
DESCRIPTION
Input Address Input
Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable
Input/ Output Data Input/ Output
Supply Power, 5V
Ground Ground
- No Connect
Taiwan Memory Technology, Inc. reserves the right P. 2
to change products or specifications without notice.
Publication Date:AUG. 2000
Revision:L
DataSheet4 U .com
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( taiwan )
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