파트넘버.co.kr MTV118 데이터시트 PDF


MTV118 반도체 회로 부품 판매점

On-Screen-Display



Myson 로고
Myson
MTV118 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MYSON
MTV118
TECHNOLOGY
On-Screen-Display for LCD Monitor
FEATURES
• Horizontal sync input may be up to 120 KHz.
• Acceptable wide-range pixel clock up to 96MHz
from XIN pin.
• Full-screen display consists of 15 (rows) by 30 (col-
umns) characters.
• 12 x 18 dot matrix per character.
• Total of 256 characters and graphic fonts including
248 mask ROM fonts and 8 programmable RAM
fonts.
• 8 color selection maximum per display character.
• Double character height and/or width control.
• Programmable positioning for display screen cen-
ter.
• Bordering, shadowing and blinking effect.
• Programmable vertical character height (18 to 71
lines) control.
• Row to row spacing register to manipulate the con-
stant display height.
• 4 programmable background windows with multi-
level operation.
• Software clears for display frame.
• Half tone and fast blanking output.
• 8-channel/8-bit PWM D/A converter output.
• Compatible with SPI bus or I2C interface with
address 7AH (slave address is mask option).
• 16 or 24-pin PDIP/SOP package.
BLOCK DIAGRAM
GENERAL DESCRIPTION
MTV118 is designed for LCD monitor appli-
cations to display the built-in characters or fonts
onto an LCD monitor screen. The display oper-
ates by transferring data and control information
from the micro controller to the RAM through a
serial data interface. It can execute full screen
displays automatically and specific functions such
as character bordering, shadowing, blinking, dou-
ble height and width, font by font color control,
frame positioning, frame size control by character
height and windowing effect. Moreover, MTV118
also provides 8 PWM DAC channels with 8-bit
resolution and a PWM clock output for external
digital-to-analog control.
SSB
SCK
SDA
VFLB
HFLB
NC
XIN
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
CLOCK
GENERATOR
VCLKX
PWM D/A
CONVERTER
8 DATA
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM LUMA
USER FONT RAM
BORDER
LUMINANCE &
BORDGER
GENERATOR
DATA 8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOR
ENCODER
POWER ON
PRB
RESET
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of
the product.
1/15
MTV118 Revision 2.0 01/01/1999
DataSheet4 U .com


MTV118 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
MTV118
VSS 1
16 VSS
XIN 2
15 ROUT
NC 3
14 GOUT
VDD 4
13 BOUT
MTV118
HFLB 5
12 FBKG
SSB 6
11 HTONE/PWMCK
SDA 7
10 VFLB
SCK 8
9 VDD
VSS
XIN
NC
VDD
HFLB
SSB
SDA
SCK
PWM0
PWM1
PWM2
PWM3
1 24
2 23
3 22
4 21
5 20
6 19
MTV118N24
7 18
8 17
9 16
10 15
11 14
12 13
VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD
PWM7
PWM6
PWM5
PWM4
2.0 PIN DESCRIPTIONS
Name
VSS
XIN
NC
VDD
HFLB
SSB
SDA
SCK
PWM0
PWM1
PWM2
Pin #
I/O
N16 N24
Descriptions
- 1 1 Ground. This ground pin is used for internal circuitry.
Pixel Clock Input. This is a clock input pin. MTV118 is driven by
I 2 2 an external pixel clock source for all the logics inside. The fre-
quency of XIN must be the integral time of pin HFLB.
I 3 3 No connection.
Power supply. Positive 5 V DC supply for internal circuitry. A
- 4 4 0.1uF decoupling capacitor should be connected across VDD and
VSS.
Horizontal Input. This pin is used to input the horizontal synchro-
I 5 5 nizing signal. It is a leading edge trigger and has an internal pull-
up resistor.
Serial Interface Enabler. It is used to enable the serial data and
I 6 6 is also used to select the operation of I2C or SPI bus. If this pin is
left floating, I2C bus is enabled, otherwise the SPI bus is enabled.
Serial Data Input. The external data transfers through this pin to
I 7 7 internal display registers and control registers. It has an internal
pull-up resistor.
I 8 8 Serial Clock Input. The clock-input pin is used to synchronize the
data transfer. It has an internal pull-up resistor.
O
-
9
Open-Drain PWM D/A Converter 0. The output pulse width is
programmable by the register of row 15, column 19.
Open-Drain PWM D/A Converter 1. The output pulse width is
O - 10 programmable by the register of row 15, column 20.
Open-Drain PWM D/A Converter 2. The output pulse width is
O - 11 programmable by the register of row 15, column 21.
2/15
MTV118 Revision 2.0 01/01/1999
DataSheet4 U .com




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