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PDF PH2625L Data sheet ( Hoja de datos )
| Número de pieza | PH2625L | |
| Descripción | N-channel TrenchMOS-TM logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PH2625L
N-channel TrenchMOS™ logic level FET
Rev. 02 — 24 February 2005
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
s Optimized for use in DC-to-DC
converters
s Low threshold voltage
s Very low switching and conduction
losses
s Low thermal resistance.
1.3 Applications
s DC-to-DC converters
s Voltage regulators
s Switched-mode power supplies
s Notebook computers.
1.4 Quick reference data
www.DataSheet4U.coms VDS ≤ 25 V
s ID ≤ 100 A
s Qgd = 7.3 nC (typ)
s Qg(tot) = 32 nC (typ)
s RDSon ≤ 2.8 mΩ (VGS = 10 V)
s RDSon ≤ 4.1 mΩ (VGS = 4.5 V).
2. Pinning information
Table 1:
Pin
1, 2, 3
4
mb
Pinning
Description
source
gate
mounting base; connected to drain
Simplified outline
mb
Symbol
D
G
mbb076 S
1234
SOT669 (LFPAK)
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Philips Semiconductors
PH2625L
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
25 -
VGS(th) gate-source threshold voltage
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1 1.5
Tj = 150 °C
0.5 -
Tj = −55 °C
--
IDSS drain-source leakage current
VDS = 25 V; VGS = 0 V
Tj = 25 °C
- 0.06
Tj = 150 °C
--
RG gate resistance
f = 1 MHz
- 1.5
IGSS gate-source leakage current
VGS = ±16 V; VDS = 0 V
- 10
RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Figure 6 and 8
Tj = 25 °C
-2
Tj = 150 °C
- 3.2
www.DataSheet4U.comVGS = 4.5 V; ID = 25 A; Figure 6 and 8
Tj = 25 °C
-3
Tj = 150 °C
- 4.8
Dynamic characteristics
-
2
-
2.2
1
500
-
100
2.8
4.3
4.1
6.6
Qg(tot)
total gate charge
Qgs gate-source charge
Qgs1
pre-VGS(th) gate-source charge
Qgs2
post-VGS(th) gate-source charge
Qgd gate-drain (Miller) charge
Vplat
plateau voltage
Qg(tot)
total gate charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
Ciss input capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Figure 11 and 12
ID = 0 A; VDS = 0 V; VGS = 4.5 V
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Figure 13 and 14
VGS = 0 V; VDS = 0 V; f = 1 MHz
VDS = 12 V; RL = 0.48 Ω; VGS = 4.5 V;
RG = 4.7 Ω
- 32 -
- 9.6 -
- 6-
- 3.6 -
- 7.3 -
- 2.2 -
- 26 -
- 4308 -
- 1137 -
- 439 -
- 4830 -
- 41 -
- 52 -
- 67 -
- 30 -
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 15
- 0.85 1.2
trr reverse recovery time
Qr recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V; - 47 -
VR = 25 V
- 22 -
Unit
V
V
V
V
µA
µA
Ω
nA
mΩ
mΩ
mΩ
mΩ
nC
nC
nC
nC
nC
V
nC
pF
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
9397 750 14324
Preliminary data sheet
Rev. 02 — 24 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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Philips Semiconductors
PH2625L
N-channel TrenchMOS™ logic level FET
9. Revision history
Table 6: Revision history
Document ID Release date Data sheet status Change notice Doc. number
Supersedes
PH2625L_2
Modifications:
PH2625L-01
20050224
Preliminary data -
sheet
9397 750 14324 PH2625L-01
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• RDSon data revised in Section 1.4 “Quick reference data” and Section 6 “Characteristics”
20040428
Preliminary data -
sheet
9397 750 12306 -
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9397 750 14324
Preliminary data sheet
Rev. 02 — 24 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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