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PDF 74C32 Data sheet ( Hoja de datos )
| Número de pieza | 74C32 | |
| Descripción | MM74C32 | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74C32 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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October 1987
Revised May 2002
MM74C32
Quad 2-Input OR Gate
General Description
The MM74C32 employs complementary MOS (CMOS)
transistors to achieve low power and high noise margin,
these gates provide the basic functions used in the imple-
mentation of digital integrated circuit systems. The N- and
P-channel enhancement mode transistors provide a sym-
metrical circuit with output swings essentially equal to the
supply voltage. This results in high noise immunity over a
wide supply voltage range. No DC power other than that
caused by leakage current is consumed during static con-
ditions. All inputs are protected against static discharge
damage.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45V VCC (typ.)
s Low power TTL compatibility: fan out of 2 driving 74L
Ordering Code:
Order Number Package Number
Package Description
MM74C32M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74C32N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
© 2002 Fairchild Semiconductor Corporation DS005881
www.fairchildsemi.com
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet 74C32.PDF ] | |
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