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PDF M25P128 Data sheet ( Hoja de datos )
| Número de pieza | M25P128 | |
| Descripción | 128 Mbit (Multilevel) Low Voltage Serial Flash Memory With 50MHz SPI Bus Interface | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M25P128
128 Mbit (Multilevel), Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
PRELIMINARY DATA
Feature summary
■ 128 Mbit of Flash Memory
■ Page Program (up to 256 Bytes) in 2.5ms
(typical)
■ Sector Erase (2Mbit)
■ Bulk Erase (128Mbit)
■ 2.7 to 3.6V Single Supply Voltage
VDFPN8 (ME)
8x6mm (MLP8)
■ SPI Bus Compatible Serial Interface
■ 50MHz Clock Rate (maximum)
■ Electronic Signature
– JEDEC Standard Two-Byte Signature
(2018h)
■ More than 10000 Erase/Program Cycles per
Sector
SO16 (MF)
300 mils width
■ More than 20-Year Data Retention
www.DataSheet4U.com■ Packages
– ECOPACK® (RoHS compliant)
January 2006
Rev. 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/41
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M25P128
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VDFPN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI Modes Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . 18
Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 20
Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence. . . . . . . . . . . . . 23
Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence . . 24
Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 35
Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline 37
www.DataSheet4U.comSO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 38
Rev. 1
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M25P128
Operating features
4.5 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P128 features the following data protection mechanisms:
● Power On Reset and an internal timer (tPUW) can provide protection against inadvertant
changes while the power supply is outside the operating specification.
● Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
www.DataSheet4U.com– Bulk Erase (BE) instruction completion
● The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
● The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
Table 2. Protected Area Sizes
Status Register Content
Memory Content
BP2 Bit BP1 Bit BP0 Bit
Protected Area
Unprotected Area
0 0 0 none
All Sectors (Sectors 0 to 63)(1)
0 0 1 Upper 64th (1 Sector, 2Mb)
Sectors 0 to 62
0
1
0 Upper 32nd (2 Sectors, 4Mb)
Sectors 0 to 61
0
1
1 Upper 16nd (4 Sectors, 8Mb)
Sectors 0 to 59
1
0
0 Upper 8nd (8 Sectors, 16Mb)
Sectors 0 to 55
1 0 1 Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)
1 1 0 Upper Half (32 Sectors, 64Mb) Lower Half (Sectors 0 to 31)
1 1 1 All sectors (64 Sectors, 128Mb) none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Rev. 1
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M25P128.PDF ] | |
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