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UG09 반도체 회로 부품 판매점

(UG01 - UG09) 0.6um ULC



Temic 로고
Temic
UG09 데이터시트, 핀배열, 회로
www.DataSheet4U.com
0.6µm ULC Series
UG Series
Description
The UG series of ULCs is well suited for conversion of
medium- to-large sized CPLDs and FPGAs. Devices are
implemented in high-performance CMOS technology
with 0.6-µm (drawn) channel lengths, and are capable of
supporting flip-flop toggle rates of 350 MHz, operating
clock frequencies up to 150 MHz and input to output
delays as fast as 5 ns.
The architecture of the UG series allows for efficient
conversion of many PLD architectures and FPGA
device types. A compact RAM cell, along with the large
number of available gates allows the implementation of
RAM in FPGA architectures that support this feature, as
well as JTAG boundary-scan and scan-path testing.
Conversion to the UG series of ULC can provide a
significant reduction in operating power when
compared to the original PLD or FPGA. This is
especially true when compared to many PLD and CPLD
architecture devices, which typically consume 100 mA
or more even when not being clocked. The UG series has
a very low standby consumption of 0.4 nA/gate
typically, which would yield a standby current of 4 mA
on a 10,000 gate design. Operating consumption is a
strict function of clock frequency, which typically
results in a power reduction of 50% to 90% depending
on the device being compared.
The UG series provides several options for output
buffers, including a variety of drive levels up to 24 mA.
Schmitt trigger inputs are also an option. A number of
techniques are used for improved noise immunity and
reduced EMC emissions, including: several
independent power supply busses and internal
decoupling for isolation; slew rate limited outputs are
also available as required.
The UG series is designed to allow conversions of high
performance 3.3V devices as well as 5.0V devices.
Support of mixed supply conversions is also possible,
allowing optimal trade-offs between speed and power
consumption.
Features
D High performance ULC family suitable for
medium- to large-sized CPLDs and FPGAs
D Conversions to over 200,000 FPGA gates
D Pin counts to over 300 pins
D Any pin-out matched due to limited number of
dedicated pads
D Advanced 0.6-µm (drawn)/0.45-µm (effective)
feature size
D Triple-layer or dual-layer metal CMOS
technology
D High speed performance:
– 250-ps typical cell delay
– 350-MHz toggle rate
D Full range of packages: DIP, SOIC, LCC/PLCC,
PQFP/TQFP, PGA/PPGA
D 3.3V and/or 5.0V operation.
D Low quiescent current: 0.4 nA/gate
D Available in commercial, industrial, automotive,
military and space grades.
www.DataSheet4U.com
Rev. B 25 May. 98
5–1


UG09 데이터시트, 핀배열, 회로
www.DataSheet4U.com
UG Series
Product Outline
Part Number
UG01
UG04
UG09
UG14
UG20
UG33
UG42
UG52
UG70
UG90
UG120
UG140
Architecture
Full programmables Pads
30
48
72
88
104
130
146
162
188
212
244
264
The basic element of the UG family is called a cell. One
cell can typically implement between two to three FPGA
gates. Cells are located contiguously through out the
core of the device, with routing resources provided in
two or three metal layers above the cells. Some cell
blockage does occur due to routing, and utilization will
be significantly greater with three metal routing than
two. The sizes listed in the Product Outline are
estimated usable amounts using three metal layers. I/O
cells are provided at each pad, and may be configured as
inputs, outputs, I/Os, VDD or VSS as required to match
any FPGA or PLD pinout. Special function cells and
pins are located in the corners which typically are
unused.
In order to improve noise immunity within the device,
separate VDD and VSS busses are provided for the
internal cells and the I/O cells.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or
Schmitt Trigger, with or without a pull up or pull down
resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 3 to 12 mA
according to the chosen option. 24mA achievable, using
2 pads.
Equivalent FPGA Gates
Maximum Drive
3300
7500
15800
24300
34800
46000
58600
63700
85800
108500
145100
156800
N/A
310
790
1210
1740
2880
3660
4550
6130
7750
10360
12250
Slew Rate Controlled Output Buffer
In this mode, the p- and n-output transistor commands
are delayed, so that they are never set “ON”
simultaneously, resulting in a low switching current and
low noise. These buffer are dedicated to very high load
drive.
3.3V Compatibility
The UG series of ULCs is fully capable of supporting
high-performance operation at 3.3V or 5.0V. The
performance specifications of any given ULC design
however, must be explicitly specified as 3.3V, 5.0V or
both.
Power Supply and Noise Protection
In order to improve the noise immunity of the UG series,
several mechanisms have been implemented inside the
UG devices. Two kinds of protection have been added:
one to limit the I/O buffer switching noise and the other
to protect the I/O buffers against the switching noise
coming from the core.
I/O buffers switching protection
Three features are implemented to limit the noise
generated by the switching current: The power supplies
of the input and output buffer are separated. The rise and
fall times of the output buffers can be controlled. The
number of buffers that are connected on the same power
supply line is limited.
www.DataSheet4U.com
5–2 Rev. B 25 May. 98




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