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PDF D74HC138C Data sheet ( Hoja de datos )
| Número de pieza | D74HC138C | |
| Descripción | CD74HC138C | |
| Fabricantes | ETC | |
| Logotipo |  |
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Data sheet acquired from Harris Semiconductor
SCHS147A
October 1997 - Revised February 1999
CD74HC138, CD74HCT138,
CD74HC238, CD74HCT238
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
Features
[ /Title
(CD74
HC138
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
, • Typical Propagation Delay
CwwDw7.D4ataSheet4U.CcoLm= 15pF, TA = 25oC
of
13ns
at
VCC
=
5V,
HCT13
8,
CD74
HC238
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
(Y7) Y7 7
GND 8
16 VCC
15 Y0 (Y0)
14 Y1 (Y1)
13 Y2 (Y2)
12 Y3 (Y3)
11 Y4 (Y4)
10 Y5 (Y5)
9 Y6 (Y6)
Signal names in parentheses are for ’HC238 and ’HCT238.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 1999, Texas Instruments Incorporated
1
1 page  
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
DC Electrical Specifications (Continued)
PARAMETER
HCT TYPES
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA)
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
High Level Input
Voltage
VIH -
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
VIL
-
-
4.5 to
-
- 0.8 - 0.8 -
0.8 V
5.5
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 -
- 4.4 - 4.4
-
V
High Level Output
www.DataSheet4UV.ocltoamge
TTL Loads
-4
4.5 3.98 -
- 3.84 -
3.7
-
V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02
4.5
-
- 0.1 - 0.1 -
0.1 V
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
4
4.5 -
- 0.26 - 0.33 -
0.4 V
II
VCC and
0
GND
5.5 -
±0.1 - ±1 - ±1 µA
Quiescent Device
Current
ICC VCC or 0
GND
5.5 -
-8
- 80
- 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC
VCC
-2.1
-
4.5 to
-
100 360
-
450
-
490 µA
5.5
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A2
1.5
E1, E2
1.25
E3 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay
Address to Output
TEST
25oC
SYMBOL CONDITIONS VCC (V) MIN TYP MAX
tPLH, tPHL CL = 50pF
CL = 15pF
CL = 50pF
2 - - 150
4.5 - - 30
5 - 13 -
6 - - 26
-40oC TO
85oC
-55oC TO 125oC
MIN MAX MIN MAX UNITS
- 190 -
- 38
-
-- -
- 33
-
225 ns
45 ns
- ns
38 ns
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet D74HC138C.PDF ] | |
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