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ICS650R-07B 반도체 회로 부품 판매점

Broadcom Clock Source



Integrated Circuit Systems 로고
Integrated Circuit Systems
ICS650R-07B 데이터시트, 핀배열, 회로
( DataSheet : www.DataSheet4U.com )
ICS650-07B
Broadcom Clock Source
Description
Features
The ICS650-07B is a low cost, low jitter, high
performance clock synthesizer customized for
Broadcom. Using analog Phase-Locked Loop
(PLL) techniques, the device accepts a 25.00 MHz
clock or fundamental mode crystal input to
produce multiple output clocks of 25.0 MHz, two
125.0 MHz, 133.33 MHz, and a selectable
33.3/66.6 MHz clock. All output clocks are
frequency locked together. The ICS650-07B
outputs all have 0 ppm synthesis error.
Do not use the 125 MHz outputs to drive Gigabit
Ethernet SERDES. Instead, the 25 MHz clock
can be driven into our ICS601 in the X5 mode.
The ICS601 has low enough jitter and phase noise
for all popular SERDES.
Block Diagram
VDD GND
43
• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• Four fixed output clocks of 25 MHz, 133.33 MHz,
and two copies of 125 MHz
• One selectable output clock of 33.3 or 66.6 MHz
• Zero ppm synthesis error in all clocks
• PCI clock switching occurs within 1 µs
• Ideal for Broadcom’s BCM5600 chipset
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0 V to 5.5 V operating voltage
Output
Buffer
PCI CLK
PS
Clock Synthesis
and Control
Output
Buffer
125.00 MHz
Circuitry
Output
Buffer
125.00 MHz
25.00 MHz
crystal or clock
X1
X2
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
Output
Buffer
133.33 MHz
25.00 MHz
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MD S 650-07B A
1
Revision 042600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
www.DataSheet4U.com


ICS650R-07B 데이터시트, 핀배열, 회로
Pin Assignment
PS
X2
X1/ICLK
VDD
DC
GND
125M
125M
DC
133M
1
2
3
4
5
6
7
8
9
10
20 VDD
19 VDD
18 25M
17 PCICLK
16 VDD
15 OE
14 GND
13 D C
12 D C
11 GND
20 pin (150 mil) SSOP
ICS650-07B
Broadcom Clock Source
PCI CLK Output Select Table
PS PCICLK
Pin 1
Pin 17
0 33.33 MHz
1 66.66 MHz
0 = connect directly to GND
1 = connect directly to VDD
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
PS
X2
X1/ICLK
VDD
DC
GND
125M
125M
DC
133M
GND
DC
DC
GND
OE
VDD
PCICLK
25M
VDD
VDD
Type
I
XO
XI
P
-
P
O
O
-
O
P
-
-
P
I
P
O
O
P
P
Description
PCI Clock frequency select input. Determines PCI CLK output per table above.
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Don't Connect. Do not connect anything to this pin.
Connect to ground.
125.0 MHz clock output. Cannot be used for Gigabit Ethernet SERDES.
125.0 MHz clock output. Cannot be used for Gigabit Ethernet SERDES.
Don't Connect. Do not connect anything to this pin.
133.33 MHz clock output.
Connect to ground.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Connect to ground.
Output Enable. Tri-states all outputs when low. Internal pull-up.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
PCI Clock output per table above.
25.0 MHz buffered reference clock output.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Key: XI, XO = crystal connections; I = Input; O = Output; P = power supply connection
MD S 650-07B A
2
Revision 042600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com




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