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PDF 74AS04 Data sheet ( Hoja de datos )

Número de pieza 74AS04
Descripción SN74AS04
Fabricantes ETC　
Logotipo ETC Logotipo



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SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04
HEX INVERTERS
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain six independent hex
inverters. They perform the Boolean function
Y = A.
The SN54ALS04B and SN54AS04 are
characterized for operation over the full military
temperature range of – 55°C to 125°C. The
SN74ALS04B and SN74AS04 are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE
(each inverter)
INPUT OUTPUT
AY
HL
LH
SDAS063B – APRIL 1982 – REVISED DECEMBER 1994
SN54ALS04B, SN54AS04 . . . J PACKAGE
SN74ALS04B, SN74AS04 . . . D OR N PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
SN54ALS04B, SN54AS04 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
2A 4
18 6Y
NC 5
17 NC
2Y 6
16 5A
NC 7
15 NC
3A 8
14 5Y
9 10 11 12 13
logic symbol†
12
1A 1 1Y
34
2A 2Y
56
3A 3Y
98
4A 4Y
11 10
5A 5Y
13 12
6A 6Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
NC – No internal connection
logic diagram (positive logic)
1
1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
9
4A
8
4Y
11
5A
10
5Y
13
6A
12
6Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated
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74AS04 pdf
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From Output
Under Test
CL
(see Note A)
SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04
HEX INVERTERS
SDAS063B – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
VCC
Test
Point
RL
From Output
Under Test
CL
(see Note A)
RL
Test
Point
From Output
Under Test
CL
(see Note A)
7V
RL = R1 = R2
S1
R1
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
Data
Input
tsu
1.3 V
th
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
0.3 V
3.5 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
1.3 V
tw
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
tPZL
Waveform 1
S1 Closed
(see Note B)
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
1.3 V
tPHZ
1.3 V
1.3 V
tPLZ
3.5 V
0.3 V
[ 3.5 V
VOL
0.3 V
VOH
0.3 V
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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