|
|
PDF MC7457 Data sheet ( Hoja de datos )
| Número de pieza | MC7457 | |
| Descripción | RISC Microprocessor | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC7457 (archivo pdf) en la parte inferior de esta página. Total 68 Páginas | ||
|
No Preview Available !
Freescale Semiconductor
Technical Data
MPC7457EC
Rev. 6, 08/2005
MPC7457
RISC Microprocessor
Hardware Specifications
This hardware specification is primarily concerned with the
MPC7457; however, unless otherwise noted, all information here
also applies to the MPC7447. The MPC7457 and MPC7447 are
implementations of the PowerPC™ microprocessor family of
reduced instruction set computer (RISC) microprocessors. This
hardware specification describes pertinent electrical and physical
characteristics of the MPC7457. For functional characteristics of
the processor, refer to the MPC7450 RISC Microprocessor Family
User’s Manual.
To locate any published updates for this hardware specification,
refer to the website at http://www.Freescale.com.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Comparison with the MPC7455, MPC7445,
MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . 7
4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Electrical and Thermal Characteristics . . . . . . . . . . . 10
6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 41
9. System Design Information . . . . . . . . . . . . . . . . . . . 47
10. Document Revision History . . . . . . . . . . . . . . . . . . . 61
11. Part Numbering and Marking . . . . . . . . . . . . . . . . . . 63
1 Overview
The MPC7457 is the fourth implementation of the fourth
generation (G4) microprocessors from Freescale. The MPC7457
implements the full PowerPC 32-bit architecture and is targeted at
networking and computing systems applications. The MPC7457
consists of a processor core, a 512-Kbyte L2, and an internal L3
tag and controller that support a glueless backside L3 cache
through a dedicated high-bandwidth interface. The MPC7447 is
identical to the MPC7457 except that it does not support the L3
cache interface.
Figure 1 shows a block diagram of the MPC7457. The core is a
high-performance superscalar design supporting a
double-precision floating-point unit and a SIMD multimedia unit.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
Features
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set associative instruction and data caches
— Pseudo least recently used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four words per
clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding
is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding.
• Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
• Level 3 (L3) cache interface (not implemented on MPC7447)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space
— Support for 1- or 2-MB of cache space
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1-MB) or 128-byte (2-MB) sectored line size
— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-,
or 4-MB of private memory
— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined synchronous burst
SRAMs, and pipelined (register-register) late write synchronous burst SRAMs
— Supports parity on cache and tags
Freescale Semiconductor
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 6
5
5 Page 
Electrical and Thermal Characteristics
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol Maximum Value Unit Notes
Storage temperature range
Tstg –55 to 150 °C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5-V mode.
7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
9. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
10. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Figure 2 shows the undershoot and overshoot voltage on the MPC7457.
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
VIH
VIL
GND
GND – 0.3 V
GND – 0.7 V
Not to exceed 10%
of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7457 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see Table 4 for actual
recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is
selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage
will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins.
Freescale Semiconductor
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 6
11
11 Page | ||
| Páginas | Total 68 Páginas | |
| PDF Descargar | [ Datasheet MC7457.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC7457 | RISC Microprocessor | Freescale Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |