|
|
PDF STA013B Data sheet ( Hoja de datos )
| Número de pieza | STA013B | |
| Descripción | (STA013x) MPEG 2.5 LAYER III AUDIO DECODER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de STA013B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
STA013
® STA013B STA013T
MPEG 2.5 LAYER III AUDIO DECODER
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
m- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
oDECODES LAYER III STEREO CHANNELS,
.cDUAL CHANNEL, SINGLE CHANNEL
(MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAM-
PLING FREQUENCIES AND THE EXTEN-
USION TO MPEG 2.5:
t448, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
eDATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
DIGITAL VOLUME CONTROL
eDIGITAL BASS & TREBLE CONTROL
hSERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
STERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S
taAND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-
aPUT PCM CLOCK GENERATION
LOW POWER CONSUMPTION:
85mW AT 2.4V
.DCRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS
wI2C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
w10 MHz, 14.31818 MHz, OR 14.7456 MHz
EXTERNAL INPUT CLOCK OR BUILT-IN IN-
wDUSTRY STANDARD XTAL OSCILLATOR
DIFFERENT FREQUENCIES MAY BE SUP-
mPORTED UPON REQUEST TO STM
.coAPPLICATIONS
t4UPC SOUND CARDS
eeMULTIMEDIA PLAYERS
SO28
TQFP44
LFBGA64
ORDERING NUMBERS: STA013$ (SO28)
STA013T$ (TQFP44)
STA013B$ (LFBGA 8x8)
DESCRIPTION
The STA013 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5.
STA013 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Out-
put Interface. This interface is software program-
mable to adapt the STA013 digital output to the
most common DACs architectures used on the
market.
The functional STA013 chip partitioning is de-
scribed in Fig.1.
www.DataShFebruary 2004
1/38
1 page  
STA013 - STA013B - STA013T
1. ELECTRICAL CHARACTERISTICS: VDD = 2.7V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
Parameter
VDD Power Supply Voltage
Value
2.4 to 3.6V
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
IIL
IIH
Vesd
Parameter
Low Level Input Current
Without pull-up device
High Level Input Current
Without pull-up device
Electrostatic Protection
Test Condition
Vi = 0V
Vi = VDD = 3.6V
Leakage < 1µA
Min.
-10
-10
2000
Typ.
Max.
10
10
Unit
µA
µA
V
Note
1
1
2
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
VIL
VIH
Vol
Voh
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
Test Condition
Iol = Xma
Min. Typ.
0.8*VDD
0.85*VDD
Max.
0.2*VDD
0.4V
Unit
V
V
V
V
Note
1, 2
1, 2
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Ipu
Rpu
Parameter
Pull-up current
Equivalent Pull-up
Resistance
Test Condition
Vi = 0V; pin numbers 7, 24
and 26; VDD = 3V
Note 1: Min. condition: VDD = 2.4V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
Symbol
PD
Parameter
Power Dissipation
@ VDD = 3V
Test Condition
Sampling_freq ≤24 kHz
Sampling_freq ≤32 kHz
Sampling_freq ≤48 kHz
Min.
-25
Min.
Typ.
-66
50
Typ.
76
79
85
Max.
-125
Max.
Unit
µA
kΩ
Unit
mW
mW
mW
Note
1
Note
5/38
5 Page 
STA013 - STA013B - STA013T
3.4 - READ OPERATION (see Fig. 11)
3.4.1 - Current byte address read
The STA013 has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1.
The STA013 acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. How-
ever in this case the master does acknowledge
the data byte output and the STA013 continues to
output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
4 - I2C REGISTERS
The following table gives a description of the
MPEG Source Decoder (STA013) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip-
tion of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall oper-
ate reading or writing on 8 bits only.
I2C REGISTERS
HEX_COD
$00
$01
$05
$06
$07
$0B
$0C
$0D
$0F
$10
$13
$14
$16
$18
$40
$41
$42
DEC_COD
0
1
5
6
7
11
12
13
15
16
19
20
22
24
64
65
66
DESCRIPTION
VERSION
IDENT
PLLCTL [7:0]
PLLCTL [20:16] (MF[4:0]=M)
PLLCTL [15:12] (IDF[3:0]=N)
reserved
REQ_POL
SCLK_POL
ERROR_CODE
SOFT_RESET
PLAY
MUTE
CMD_INTERRUPT
DATA_REQ_ENABLE
SYNCSTATUS
ANCCOUNT_L
ANCCOUNT_H
RESET
0xAC
0xA1
0x0C
0x00
0x01
0x04
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R (8)
R (8)
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R (8)
W (8)
R/W(8)
R/W(8)
R/W(8)
R/W(8)
R (8)
R (8)
R (8)
11/38
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA013B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| STA013 | (STA013x) MPEG 2.5 LAYER III AUDIO DECODER | ST Microelectronics |
| STA013B | (STA013x) MPEG 2.5 LAYER III AUDIO DECODER | ST Microelectronics |
| STA013T | (STA013x) MPEG 2.5 LAYER III AUDIO DECODER | ST Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |