PDF KM23SV64205T Data sheet ( Hoja de datos )

Número de pieza	KM23SV64205T
Descripción	2M x 32 Synchronous Mask ROM
Fabricantes	Samsung Semiconductor
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No Preview Available ! KM23SV64205T Advance Information Synch. MROM 2Mx32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM23SV64205T is a synchronous high bandwidth mask • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16) • Switchable organization 4,194,304 x 16(word mode) / programmable ROM fabricated with SAMSUNG′s high perfor- mance CMOS process technology and is organized either as 4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double word mode) depending on polarity of WORD pin.(see pin func- 2,097,152 x 32(double word mode) tion description). Synchronous design allows precise cycle con- • All inputs are sampled at the rising edge of the system clock trol, with the use of system clock, I/O transactions are possible • Read Performance at memory point of view on every clock cycle. Range of operating frequencies, program- @33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3) @50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) m@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) @100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) o• tSAC : 6ns • MRS cycle with address key programs .c-. RAS Latency(1 & 2) -. CAS Latency(3 ~ 6) -. Burst Length : 4, 8 U-. Burst Type : Sequential & Interleaved • DQM for data-out masking t4• Package :86TSOP2 - 400 mable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. ORDERING INFORMATION Part NO. KM23SV64205T-10 KM23SV64205T-12 KM23SV64205T-15 KM23SV64205T-20 KM23SV64205T-30 MAX Freq. 100MHz 83MHz 66MHz 50MHz 33MHz Interface LVTTL Package 86TSOP2 eeFUNCTIONAL BLOCK DIAGRAM hQ0 Q16 ta. S. .Output Buffer Q15 Q31 .DaCLK wADD ww t4U.comLCKE LRAS www.DataSheeCLK CKE 2M x 32 Cell Array Column Decoder Latency & Burst Length LMR LCAS Timing Register Programming Register MR RAS CAS CS DQM * Samsung Electronics reserves the right to change products or specification without notice. 1 page KM23SV64205T Advance Information Synch. MROM AC OPERATING TEST CONDITIONS(TA = 0 to 70°C, VDD = 3.3V±0.3V, unless otherwise noted.) Parameter Timing Reference Levels of Input/Output Signals Input Signal Levels Transition Time (Rise & Fall) of Input Signals Output Load Value 1.4V VIH/VIL=2.4V/0.4V tr/tf=1ns/1ns LVTTL Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi- tion time is measured between VIL(Max) and VIH(Min). 3.3V Vtt=1.4V Output 870Ω 1200Ω VOH (DC)=2.4V, IOH=-2mA VOL (DC)=0.4V, IOL=2mA 50pF Output Z0=50Ω 50Ω 50pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETERS (AC operating conditions unless otherwise noted) Parameter CLK Cycle Time CLK to Valid Output Delay Data Output Hold Time CLK High Pulse Width CLK Low Pulse Width Row-active to Row-active Input Setup Time Input Hold Time CLK to Output in Low-Z CLK to Output in High-Z Transition Time Valid CAS Enable to Valid CAS Enable Symbol tCC tSAC tOH tCH tCL tRC tSS tSH tSLZ tSHZ tT up to 100MHz Min Max 10 -6 2- 3- 3- 10 - 2- 1- 0- -7 0.1 10 tVCVC 8 - up to 83MHz Min Max 12 -6 2- 3.5 - 3.5 - 10 - 3- 1- 0- -8 0.1 10 8- up to 66MHz Min Max 15 - -6 2- 4- 4- 8- 4- 2- 0- - 10 0.1 10 7- up to 50 Mhz Min Max 20 - -6 2- 6.5 - 6.5 - 8- 4- 2- 0- - 15 0.1 10 7- Unit Notes ns ns ns ns ns clks 1 ns ns ns ns ns clks 2 Note : 1. These tRC values are for BL=8. For BL=4, tRC=6 clks for up to 100MHz, tRC=6 clks for up to 83MHz, tRC=4 clks for up to 66MHz, tRC=4 clks for up to 50MHz, and tRC=3 clks for up to 33MHz. RAS latency increase means, a simultaneous tRC increase in the same number of cycles. ( If RAS latency is 3 clks, tRC is 12 clks for BL=8.) Refer to attached technical note for gapless operation. 2. These tVCVC values are for BL=8. For BL=4, tVCVC=4clks for up to 100MHz, tVCVC=4clks for up to 83MHz, tVCVC=3clks for up to 66MHz, tVCVC=3clks for up to 50MHz, and tVCVC=2clks for up to 33MHz. Refer to attached technical note for gapless operation. 5 Page KM23SV64205T BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. MRS Mode Register Set CLK CMD MRS Note 1 3CLK ACT 2. CLOCK Suspend Clock Suspended During Burst Read (BL=4) CLK CMD CKE Internal CLK RD Masked by CKE Data Q0 DQ01 Q2 Q3 Advance Information Synch. MROM Suspended Dout : This command do not be activated. 3. Clock Suspend Exit & power Down Exit 1) Clock Suspend Exit CLK CKE Internal CLK CMD tSS RD 2) Power Down Exit CLK CKE Internal CLK CMD tSS NOP ACT Note : 1. After mode register set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H" within a minimum of 3 clock cycles. 11 Page

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