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PDF FW21555 Data sheet ( Hoja de datos )
| Número de pieza | FW21555 | |
| Descripción | PCI-to-PCI Bridge | |
| Fabricantes | Intel | |
| Logotipo |  |
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taSh2Be1er5itd45Ug5.ecNomon-Transparent PCI-to-PCIDatasheet
ww.Da Product Featuress Full compliance with the PCI local Bus
w Specification, Revision 2.2, plus:
m—PCI Power Management support
— Vital Product Data (VPD) support
o—CompactPCI Distributed Hot-Swap
.csupport
s 3.3-V operation with 5.0-V tolerant I/O
s Selectable asynchronous or synchronous
Uprimary and secondary interface clocks
t4s Concurrent primary and secondary bus
operation
s Fully compliant with the Advanced
eConfiguration Power Interface (ACPI)
specification
es Fully compliant with the PCI Bus Power
Management specification
hs Queuing of multiple transactions in either
direction
Ss 256 bytes of posted write (data and
taaddress) buffering in each direction
s 256 bytes of read data buffering in each
direction
as Four delayed transaction entries in each
direction
.Ds Two dedicated I2O delayed transaction
entries
s Two sets of standard PCI Configuration
wregisters corresponding to the primary and
secondary interface; each set is accessible
from either the primary or secondary
winterface
ms Direct offset address translation for
w odownstream memory and I/O transactions
.cs Hardware enable for secondary bus central
functions
t4Us IEEE Standard 1149.1 boundary-scan
JTAG interface
s Four primary interface base address
configuration registers for downstream
forwarding, with size and prefetchability
programmable for all four address ranges
s Three secondary interface address
configuration registers specifying local
address ranges for upstream forwarding,
with size and prefetchability programmable
for all three address ranges
s Inverse decoding above the 4 GB address
boundary for upstream DACs
s Ability to generate Type 0 and Type 1
configuration commands on the primary or
secondary interface via configuration or I/O
CSR accesses
s Ability to generate I/O commands on the
primary or secondary interface via I/O CSR
accesses
s I2O message unit
s Doorbell registers for software generation
of primary and secondary bus interrupts, 16
bits per interface
s Eight Dwords of scratchpad registers
s Generic own bit (can memory-map)
semaphore
s Parallel flash ROM interface with primary
bus expansion ROM base address register
s Serial ROM interface
s Secondary bus arbiter support for up to
nine external devices at 33 MHz and up to
four external devices at 66 MHz (in
addition to the 21555)
s Secondary bus clock output for
synchronous operation
s Four 32-bit base address configuration
registers mapping the 21555 control and
status registers (CSRs)
s Available in 33 MHz and 66 MHz versions
heeNotice: This document contains preliminary information on new products in production. The
Sspecifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
www.DataOrder Number: 278320-002
1 page  
1.0
1.1
Non-Transparent PPB
Introduction
Intel’s 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and
intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface,
and 66-MHz capability. The 21554 a related PCI peripheral device, has a 64-bit primary interface,
a 64-bit secondary interface, and 33-MHz capability.”
The 21555 is a “non-transparent” PCI-to-PCI bridge that acts as a gateway to an intelligent
subsystem. It allows a local processor to independently configure and control the local subsystem.
The 21555 implements an I2O message unit that enables any local processor to function as an
intelligent I/O processor (IOP) in an I2O-capable system. Because the 21555 is architecture
independent, it works with any host and local processors that support a PCI bus. This architecture
independence enables vendors to leverage existing investments while moving products to PCI
technology.
Unlike a transparent PCI-to-PCI bridge, the 21555 is specifically designed to bridge between two
processor domains. The processor domain on the primary interface of the 21555 is also referred to
as the host domain, and its processor is the host processor. The secondary bus interfaces to the local
domain and the local processor. Special features include support of independent primary and
secondary PCI clocks, independent primary and secondary address spaces, and address translation
between the primary (host) and secondary (local) domains.
The 21555 enables add-in card vendors to present to the host system a higher level of abstraction
than is possible with a transparent PCI-to-PCI bridge. The 21555 uses a Type 0 configuration
header, which presents the entire subsystem as a single “device” to the host processor. This allows
loading of a single device driver for the entire subsystem, and independent local processor
initialization and control of the subsystem devices. Because the 21555 uses a Type 0 configuration
header, it does not require hierarchical PCI-to-PCI bridge configuration code.
The 21555 forwards transactions between the primary and secondary PCI buses as does a
transparent PCI-to-PCI bridge. In contrast to a transparent PCI-to-PCI bridge, however, the 21555
can translate the address of a forwarded transaction from a system address to a local address, or
vice versa. This mechanism allows the 21555 to hide subsystem resources from the host processor
and to resolve any resource conflicts that may exist between the host and local subsystems.
The 21555 operates at 3.3 V and is also 5.0-V I/O tolerant. Adapter cards designed using the 21555
can be keyed as universal, thus permitting use in either a 5-V or 3-V slot.
Comparing 21555 and Standard PCI-to-PCI Bridge
The 21555 is functionally similar to a standard PCI-to-PCI bridge (PPB) in that both provide a
connection path between devices attached to two independent PCI buses. A 21555 and a PPB allow
the electrical loading of devices on one PCI bus to be isolated from the other bus while permitting
concurrent operation on both buses. Because the PCI Local Bus Specification restricts PCI option
cards to a single electrical load, the ability of PPBs and the 21555 to spawn PCI buses enables the
design of multi device PCI option cards. The key difference between a PPB and the 21555 is that
the presence of a PPB in a connection path between the host processor and a device is transparent
to devices and device drivers, while the presence of the 21555 is not. This difference enables the
21555 to provide features that better support the use of intelligent controllers in the subsystem.
Datasheet
5
5 Page 
Non-Transparent PPB
Figure 3. 21555 PBGA Cavity Down View
Pin 1 Corner
A
B
C
D
E
F
G
H
J
K
L 21555
M Top View
N (Pin Down)
P
R
T
U
V
W
Y
AA
AB
AC
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A7436-01
Datasheet
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FW21555.PDF ] | |
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