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PDF NT256D64S88B0G Data sheet ( Hoja de datos )
| Número de pieza | NT256D64S88B0G | |
| Descripción | (NT256D64S88Bxx) 256MB DDR DIMM | |
| Fabricantes | Nanya Technology | |
| Logotipo |  |
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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
Based on DDR400/333/266 256M bit B Die device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 256M bit die B device,
organized as either 32Mbx8 or 16Mbx16
• Performance:
PC3200 PC2700 PC2100
Speed Sort
5T 6K 75B Unit
DIMM CAS Latency
3 2.5 2.5
fCK Clock Frequency
200 166 133 MHz
tCK Clock Cycle
5 6 7.5 ns
fDQ DQ Burst Frequency 400 333 266 MHz
• Intended for 133, 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = VDDQ = 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
• SDRAMs are packaged in TSOP packages
• “Green” packaging – lead free
Description
NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,
NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM
Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.
NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8
TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,
NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.
NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,
organized as single rank using four 16Mx16 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 2.2
Aug 3, 2004
Preliminary
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
1 page  
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
2 Ranks, 16 devices, 32Mx8 DDR SDRAMs
S1
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D0
DM CS DQS
I/O 0
I/O 1
I/O 6
I/O 7 D8
I/O 2
I/O 3
I/O 4
I/O 5
DM CS DQS
I/O 7
I/O 6
I/O 1
I/O 0 D1
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D9
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D10
DQS
DM CS DQS
I/O 7
I/O 6
I/O 1
I/O 0 D3
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D11
DQS
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D12
DM CS DQS
I/O 7
I/O 6
I/O 1
I/O 0 D5
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D13
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D14
DQS
DM CS DQS
I/O 7
I/O 6
I/O 1
I/O 0 D7
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D15
DQS
BA0-BA1
A0-A13
RAS
CAS
CKE0
BA0-BA1 : SDRAMs D0-D15
A0-A13 : SDRAMs D0-D15
RAS : SDRAMs D0-D15
CAS : SDRAMs D0-D15
CKE : SDRAMs D0-D7
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
CKE1
WE
CKE : SDRAMs D8-D15
WE : SDRAMs D0-D15
SCL
WP
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
SPD
D0-D15
D0-D15
D0-D15
Strap: see Note 4
* Clock Wiring
Clock Input SDRAMs
*CK0/CK0
4 SDRAMs
*CK1/CK1
6 SDRAMs
*CK2/CK2
6 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
Serial PD
A0 A1 A2
SA0 SA1 SA2
SDA
REV 2.2
Aug 3, 2004
Preliminary
5
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
5 Page 
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT512D64S8HBxGx
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
64-71
72
73-90
91-92
93-94
95-98
99-127
PC3200 (5T)
Value
128
256
SDRAM DDR
13
10
2
x64
x64
SSTL 2.5V
5.0ns
6.0ns
Non-Parity
SR/1x(7.8us)
x8
N/A
1 Clock
2,4,8
4
2/2.5/3
0
1
Differential Clock
±0.1V Tolerance
6ns
0.70ns
7.5ns
7.5ns
15ns
10ns
15ns
40ns
256MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
55ns
70ns
8ns
0.4ns
0.50ns
Reserved
Initial
Checksum
NANYA
Assembly
Module PN
Revision
Year/Week Code
Serial Number
Reserved
Hex
80
08
07
0D
0A
02
40
00
04
50
60
00
82
08
00
01
0E
04
1C
01
02
20
00
60
70
75
75
3C
28
3C
28
40
60
60
40
40
00
37
46
20
28
50
00
00
8F
7F7F7F0B
00000000
--
--
--
--
--
--
PC2700 (6K)
Value
128
256
SDRAM DDR
13
10
2
x64
x64
SSTL 2.5V
6.0ns
7.0ns
Non-Parity
SR/1x(7.8us)
x8
N/A
1 Clock
2,4,8
4
2/2.5
0
1
Differential Clock
±0.2V Tolerance
7.5ns
0.70ns
N/A
N/A
18ns
12ns
18ns
42ns
256MB
0.75ns
0.75ns
0.45ns
0.45ns
Reserved
60ns
72ns
12ns
0.4ns
0.55ns
Reserved
Initial
Checksum
NANYA
Assembly
Module PN
Revision
Year/Week Code
Serial Number
Reserved
Hex
80
08
07
0D
0A
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
00
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
28
55
00
00
3C
7F7F7F0B
00000000
--
--
--
--
--
--
PC2100 (75B)
Value
128
256
SDRAM DDR
13
10
2
x64
x64
SSTL 2.5V
7.5ns
7.5ns
Non-Parity
SR/1x(7.8us)
x8
N/A
1 Clock
2,4,8
4
2/2.5
0
1
Differential Clock
±0.2V Tolerance
10ns
0.75ns
N/A
N/A
20ns
15ns
20ns
45ns
256MB
0.90ns
0.90ns
0.50ns
0.50ns
Reserved
65ns
75ns
12ns
0.5ns
0.75ns
Reserved
Initial
Checksum
NANYA
Assembly
Module PN
Revision
Year/Week Code
Serial Number
Reserved
Hex
80
08
07
0D
0A
02
40
00
04
75
75
00
82
08
00
01
0E
04
0C
01
02
20
00
A0
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
23
7F7F7F0B
00000000
--
--
--
--
--
--
REV 2.2
Aug 3, 2004
Preliminary
11
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NT256D64S88B0G.PDF ] | |
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