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S3076TT 반도체 회로 부품 판매점

Multi-Rate Sonet/SDH Clock Recovery Unit



Applied Micro Circuits 로고
Applied Micro Circuits
S3076TT 데이터시트, 핀배열, 회로
®
mDEVICE
.coSMPEUCLITFIIC-RATAIOTEN SONET/SDH CLOCK RECOVERY UNIT
BMiUCLMTOI-SRAPTEECLSOCNLEOTC/KSDGHECNLEORCAKTORRECOVERY UNIT
S3076
S3076
et4UFEATURES
he• SiGe BiCMOS technology
S• Complies with Bellcore and ITU-T specifica-
tations for jitter tolerance, jitter transfer and
ajitter generation
.D• On-chip high frequency PLL with internal
w loop filter for clock recovery
w • Supports clock recovery for:
w OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
mOC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
oFibre Channel (1062.5 Mbps) (with FEC)
.cOC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps) (with FEC) NRZ data
• Selectable reference frequencies
U19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
t4Gigabit Ethernet frequencies)
• Lock detect—monitors frequency of
eincoming data
e• Low-jitter serial interface
• +3.3 V supply
h• Compact 48 pin TQFP TEP package
S• Typical power 620 mW
• Available in Die form also
GENERAL DESCRIPTION
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3076 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
ataFigure 1. System Block Diagram
.D16 16
OTX
ORX S3076
wS3057
w16
w www.DataSheet4U.comS3076 ORX
OTX
S3057
16
October 23, 2000 / Revision A
1


S3076TT 데이터시트, 핀배열, 회로
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076 OVERVIEW
The S3076 supports clock recovery for the OC-48,
Fibre Channel (2125 Mbps), OC-24, Gigabit
Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or
OC-3 data rate with FEC capabilty up to 8 bytes per
255-byte block. Differential serial data is input to the
chip at the specified rate, and clock recovery is per-
formed on the incoming data stream. An external os-
cillator is required to minimize the PLL lock time, and
provide a stable output clock source in the absence of
serial input data. Retimed data and clock are output
from the S3076.
Suggested Interface Devices
Sumitomo
OC-48 Optical Receiver
AMCC S3057
OC-48 Transceiver
Figure 2. S3076 Functional Block Diagram
CAP 1,2
2
LOOP
FILTER
VCO
TESTOUT
REFCLKP/N
TESTCLK
RATESEL[1:0]
REFSEL
TESTEN
LCKREFN
2
RST
SDN
SERDATIP/N
BYPASS
CLOCK
DIVIDER
REFCMP
LOCK
DETECTOR
SERCLKOP/N
LOCKDET
PHASE DETECTOR
SERDATOP/N
2 October 23, 2000 / Revision A




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S3076TT

Multi-Rate Sonet/SDH Clock Recovery Unit - Applied Micro Circuits