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PDF 21143-TD Data sheet ( Hoja de datos )
| Número de pieza | 21143-TD | |
| Descripción | Upgrading to the 21143-PD and 21143-TD Application Note | |
| Fabricantes | Intel | |
| Logotipo |  |
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www.DataSheUept4gU.rcaodming to the 21143-PD and
m21143-TD
.coApplication Note
November 1998
www.DataSheet4Uwww.DataSheet4U.comOrder Number: 278232-001
1 page  
1.0
1.1
1.2
Upgrading to the 21143-PD and 21143-TD
Introduction
The purpose of this document is to provide customers of the 21143 family with information to
upgrade to its newest and most powerful members, the 21143–PD and the 21143–TD.
This document describes how to upgrade your designs from the 21143–PC and 21143–TC, to the
21143–PD and 21143–TD. It also describes register-level differences, and serves as a convenient
reference for upgrading customer-developed drivers. For detailed programming information and
for register descriptions, consult the 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller
Hardware Reference Manual (order number 278074).
Advantages of Upgrading to the 21143-xD
The 21143-PD and 21143-TD are pin compatible and are the functional equivalent of the 21143-PC
and 21143-TC. However, they offer the following additional features and performance enhancements:
• Support network device class OnNow requirements for Microsoft’s PC 97 and PC 98
specifications, including all wake-up events:
— Pattern matching
— Link change
— Magic Packet
• Fully compliant with Advanced Configuration and Power Interface (ACPI) Specification,
Revision 1.0.
• Fully compliant with PCI Bus Power Management Interface specification, Revision 1.0.
• Support PCI/CardBus clock control through clkrun.
• Support CardBus cstschg pin and Status Changed registers.
• Support interrupt mitigation on transmit and receive.
• Improve power consumption in sleep and snooze modes.
• Support the electrical requirements of both PCI and CardBus pads.
• Support storage of CardBus Card Information Structure (CIS), also known as tuples, in the
serial ROM or the external flash ROM.
• Provide a link indication for the 10BASE-T and the 100BASE-TX symbol interface on the same
pin. The LED is On when a valid link is established, and Off when a valid link is not found.
• Implement stretcher circuitry for the activity LED. This enables direct connection of the
21143-xD pin to the LED without the need for an external stretcher circuit.
• Provide link and activity indications on the same pin.
• Implement signal-detection filtering to avoid false detection of a link in the 100BASE-TX
symbol interface.
• Provide three new PCI configuration registers.
• Provide two new control status registers.
• Implement fixes to erratas of the 21143-PC and 21143-TC.
Physical Features of the 21143-PD and 21143-TD
The 21143-PD and 21143-TD have the same body size and pin count as the 21143-PC and
21143-TC, making them drop-in replacements.
Application Note
1
5 Page 
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 2 of 6)
New or Different
Items
21143-xC Registers
CCID<19>
Not present
CCID<21>
CCID<25>
CCID<26>
CCID<27>
CCID<28>
CCID<29>
CCID<30>
Not present
Not present
Not present
Not present
Not present
Not present
Not present
CCID<31>
CPMC
Not present
Not present
CPMC<1:0>
Not present
CPMC<8>
Not present
CPMC<15>
Not present
21143-xD Registers
Power Management Event Clock. The value of this
field is 0, indicating that the 21143-xD does not rely on
the presence of the PCI/CardBus clock in order to
generate a PME.
Device Specific Initialization. The value of this field is
0, indicating that the 21143-xD does not require a
special initialization code sequence in order to be
configured correctly.
D1 Support. The value of this field is 1, indicating that
the 21143-xD supports the D1 power state.
D2 Support. The value of this field is 1, indicating that
the 21143-xD supports the D2 power state.
PME Support D0. The value of this field is 0, indicating
the 21143-xD does not assert PME in D0 power state.
PME Support D1. The value of this field is 1, indicating
that the 21143-xD may assert PME in D1 power state.
PME Support D2. The value of this field is 1, indicating
that the 21143-xD may assert PME in D2 power state.
PME Support D3hot. The value of this field is 1,
indicating the 21143-xD may assert PME in D3hot
power state.
PME Support D3cold. If this bit is set, the 21143-xD
may assert PME in D3cold power state. Otherwise, the
21143-xD may not assert PME inD3cold. The value of
this bit is loaded from Func0_HwOptions<6> bit in the
serial ROM.
Power Management Control and Status Register.
Offset E0h.
Power State. This field is used to set the current power
state of the 21143-xD and to determine its power state.
The definition of the field values are:
0 - D0
1 - D1
2 - D2
3 - D3hot
This field gets a value of 0 after power-up.
PME_Enable. If this bit is set the 21143-xD can assert
the gep<2>/rcv_match/wake pin. Otherwise, the
assertion of the gep<2>/rcv_match/wake pin by the
21143-xD is disabled.
This bit is cleared on power-up reset only, and is not
modified by either hardware or software reset.
PME_Status. This bit indicates that the 21143-xD has
detected a power-management event. If the
PME_Enable bit is set, the 21143-xD also asserts the
gep<2>/rcv_match/wake pin.
This bit is cleared on power-up reset or by write 1. It is
not modified by either a hardware or software reset.
When this bit is cleared the 21143-xD deasserts the
gep<2>/rcv_match/wake pin.
NOTE: This bit is also cleared if the General Enable
bit of the FER (FER<4>) is cleared.
Application Note
7
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 21143-TD.PDF ] | |
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