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PDF ST93C06 Data sheet ( Hoja de datos )
| Número de pieza | ST93C06 | |
| Descripción | 256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST93C06 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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ST93C06
ST93C06C
256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 16 x 16 or 32 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE 5V ±10% SUPPLY VOLTAGE
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCES for ”C” VERSION
ST93C06 and ST93C06C are replaced by
the M93C06
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93C06 and ST93C06C are 256 bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. In the text the
two products are referred to as ST93C06.
The memory is divided into either 32 x 8 bit bytes
or 16 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
The memory is accessed through a serial input (D)
and by a set of instructions which includes Read a
byte/word, Write a byte/word, Erase a byte/word,
Erase All and Write All. ARead instruction loads the
address of the first byte/word to be read into an
internal address pointer.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG
Organisation Select
VCC Supply Voltage
VSS Ground
D
C
S
ORG
VCC
ST93C06
ST93C06C
VSS
Q
AI00816B
June 1997
This is information on a product still in production bu t not recommended for new de signs.
1/15
1 page  
Figure 5. Synchronous Timing, Read or Write
ST93C06, ST93C06C
C
S
tDVCH
tCHDX
D An
A0
Hi-Z
Q
tCHQL
ADDRESS INPUT
tCHQV
Q15/Q7
tCLSL
tSLSH
tSLQZ
Q0
DATA OUTPUT
AI00820C
C
S
tDVCH
D An
Hi-Z
Q
tCHDX
A0/D0
ADDRESS/DATA INPUT
tSLCH
tCLSL
tSLSH
tSHQV tSLQZ
BUSY
READY
tW
WRITE CYCLE
AI01429
DESCRIPTION (cont’d)
The DU (Don’t Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
MEMORY ORGANIZATION
The ST93C06 is organized as 32 bytes x 8 bits or
16 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C06 is in standby mode, the ORG input
should be unconnected or set to either VSS or VCC
in order to achieve the minimum power consump-
tion. Any voltage between VSS and VCC applied to
ORG may increase the standby current value.
5/15
5 Page 
Figure 11. WRITE Swquence with One Clock Glitch
ST93C06, ST93C06C
S
C
D
START
”0” ”1”
WRITE
An
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395
DIFFERENCES BETWEEN ST93C06 AND
ST93C06C (cont’d)
The ST93C06C is an enhanced version of the
ST93C06A and offers the following extra features:
– Enhanced ESD voltage
– Functional security filtering glitches on the
clock input (C).
Refer to Table 2 (Absolute Maximum Ratings) for
more about ESD limits. The following description
will detail the Clock pulses counter (available only
on the ST93C06C).
In a normal environment, the ST93C06 is expected
to receive the exact amount of data on the D input,
that is the exact amount of clock pulses on the C
input.
In a noisy environment, the amount of pulses re-
ceived (on the clock input C) may be greater than
the clock pulses delivered by the Master (Microcon-
troller) driving the ST93C06C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 11), and it may induce an erroneous write of
data at a wrong address.
The ST93C46C has an on-board counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 18 (with
the Organisation by 8) from the Start bit to the
falling edge of Chip Select signal (1 Start bit + 2 bits
of Op-code + 7 bits of Address + 8 bits of Data =
18): if so, the ST93C06C executes the WRITE
instruction; if the number of clock pulses is not
equal to 18, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisation by 16 is
selected, the number of clock pulses incoming to
the counter must be exactly 25 (1 Start bit + 2 bits
of Op-code + 6 bits of Address + 16 bits of Data =
25) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C06C executes the
WRITE instruction; if the number of clock pulses is
not equal to 25, the instruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions (WRITE, ERASE, ERAL, WRALL).
11/15
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ST93C06.PDF ] | |
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