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PDF ST6200C Data sheet ( Hoja de datos )
| Número de pieza | ST6200C | |
| Descripción | 8-BIT MCU | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST6200C ST6201C ST6203C
8-bit MCUs with A/D converter,
two timers, oscillator safeguard & safe reset
■ Memories
– 1K or 2K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
■ Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage detector (LVD) for safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
– Oscillator safeguard (OSG)
– 2 Power saving modes: Wait and Stop
■ Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 9 external interrupt lines (on 2 vectors)
■ 9 I/O Ports
– 9 multifunctional bidirectional I/O lines
– 4 alternate function lines
– 3 high sink outputs (20mA)
■ 2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
■ Analog Peripheral
– 8-bit ADC with 4 input channels (except on
ST6203C)
■ Instruction Set
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
PDIP16
SO16
SSOP16
CDIP16W
(See Section 11.5 for Ordering Information)
■ Development Tools
– Full hardware/software development package
Device Summary
Features
ST6200C
ST6201C
ST6203C
Program memory - bytes
1K
2K
RAM - bytes
Operating Supply
64
3.0V to 6V
Analog Inputs
4
Clock Frequency
Operating Temperature
Packages
8MHz Max
-40°C to +125°C
PDIP16 / SO16 / SSOP16
1K
-
October 2009
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Table of Contents
11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3 ECOPACK INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6.2ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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ST6200C ST6201C ST6203C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
080h
to 083h
0C0h
0C1h
CPU
I/O Ports
X,Y,V,W
DRA 1) 2) 3)
DRB 1) 2) 3)
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
xxh R/W
00h R/W
00h R/W
0C2h
0C3h
0C4h
0C5h
I/O Ports
DDRA 2)
DDRB 2)
Reserved (2 Bytes)
Port A Direction Register
Port B Direction Register
00h R/W
00h R/W
0C6h
0C7h
Reserved (2 Bytes)
0C8h
CPU
IOR
Interrupt Option Register
xxh Write-only
0C9h
ROM
DRWR
Data ROM Window register
xxh Write-only
0CAh
0CBh
0CCh
0CDh
I/O Ports
ORA 2)
ORB 2)
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
00h R/W
00h R/W
0CEh
0CFh
Reserved (2 bytes)
0D0h
0D1h
ADC
ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh Read-only
40h Ro/Wo
0D2h
0D3h
0D4h
Timer 1
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
7Fh
0FFh
00h
R/W
R/W
R/W
0D5h
to 0D7h
Reserved (3 Bytes)
0D8h
Watchdog
Timer
WDGR
Watchdog Register
0FEh R/W
0D9h
to 0FEh
Reserved (38 Bytes)
0FFh
CPU
A
Accumulator
xxh R/W
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 7 "I/O PORTS" on page 36 for more details).
4. Depending on device. See device summary on page 1.
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| PDF Descargar | [ Datasheet ST6200C.PDF ] | |
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