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PDF SY100EL14V Data sheet ( Hoja de datos )
| Número de pieza | SY100EL14V | |
| Descripción | 5V/3.3V 1:5 Clock Distribution | |
| Fabricantes | Micrel Semiconductor | |
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SY100EL14V
5V/3.3V 1:5 Clock Distribution
General Description
The SY100EL14V is a low-skew, 1:5 clock distribution chip
designed explicitly for low-skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. The EL14V is
suitable for operation in systems operating with 3.3V to
5.0V supplies. If a single-ended input is to be used, the
VBB output should be connected to the /CLK input and
bypassed to ground via a 0.01µF capacitor. The VBB output
is designed to act as the switching reference for the input
of the EL14V under single-ended input conditions. As a
result, this pin can only source/sink up to 0.5mA of current.
The EL14V features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left open
and pulled LOW by the input pull-down resistor), the SEL
pin will select the differential clock input.
The common enable (/EN) is synchronous, so that the
outputs will only be enabled/disable when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock.
Therefore, all associated specification limits are referenced
to the negative edge of the clock input.
When both differential inputs are left open, CLK input will
pull down to VEE and /CLK input will bias around VCC/2.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• 3.3V and 5V power supply options
• 70fsRMS typical additive phase jitter
• Typical 30ps output-to-output skew
• Max. 50ps output-to-output skew
• Synchronous enable/disable
• Multiplexed clock input
• 75kΩ internal input pull-down resistors
• Available in 20-pin SOIC package
Applications
• Processor clock distribution
• SONET clock distribution
• Fibre Channel clock distribution
• Gigabit Ethernet clock distribution
Block Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 16, 2014
Revision 5.0
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
Additive Phase Noise
VCC = +5V, TA = 25°.
SY100EL14V
October 16, 2014
5 Revision 5.0
[email protected] or (408) 955-1690
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY100EL14V.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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