파트넘버.co.kr ST92F150 데이터시트 PDF


ST92F150 반도체 회로 부품 판매점

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM / E3 TMEMULATED EEPROM / CAN 2.0B AND J1850 BLPD



ST Microelectronics 로고
ST Microelectronics
ST92F150 데이터시트, 핀배열, 회로
ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
PRELIMINARY DATA
s Memories
– Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulat-
ed EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
s Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int. clock)
s 80, 77 or 48 I/O pins (depending on device)
s Interrupt Management
– 80, 77 or 48 I/O pins (depending on device)
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
– DMA controller for reduced processor overhead
s Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
s Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
TQFP64
14x14
PQFP100
14x20
TQFP100
14x14
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only) with 13-bit LIN Synch
Break generation capability
– J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
– One or two full I²C multiple Master/Slave Interfaces
supporting Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces
s 10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
s Development Tools
– Free High performance Development environment
(IDE) based on Visual Debugger, Assembler, Linker,
and C-Compiler; Real Time Operating System (OS-
EK OS, CMX) and CAN drivers
– Hardware Emulator and Flash Programming Board
for development and ISP Flasher for production
DEVICE SUMMARY
Features
ST92F124R9 ST92F124V1 ST92F150C(R/V)1
FLASH - bytes
64K
128K
128K
RAM - bytes
E3 TM - bytes
2K
1K
4K
1K
4K
1K
Timers and Serial
Interface
2 MFT, STIM,
WD, SCI, SPI,
I²C
2 MFT, 2 EFT,
STIM, WD,
2 SCI, SPI, I²C
2 MFT, 0/2 EFT,
STIM, WD,
1/2 SCI, SPI, I²C
ADC
8 x 10 bits
16 x 10 bits
8/16 x 10 bits
Network Interface
-
CAN
Temp. Range
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C ,
-40°C to 125°C 2)
Packages
TQFP64
PQFP100
P/TQFP100 and
TQFP64
ST92F150JDV1
ST92F250CV2
128K
256K
6K 8K
1K 1K
2 MFT, 2 EFT, 2 MFT, 2 EFT, STIM,
STIM, WD,
2 SCI, SPI, I²C
WD, 2 SCI,
SPI, 2 I²C 1)
16 x 10 bits
2 CAN, J1850
CAN, LIN Master
-40o C to 125o C
-40°C to 105°C ,
-40°C to 125°C 2)
P/TQFP100
1) see Section 12.3 on page 396 for important information
2) see Table 70 on page 393
Rev. 1.3
December 2002
1/398
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 9


ST92F150 데이터시트, 핀배열, 회로
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 VOLTAGE REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 ALTERNATE FUNCTIONS FOR I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4 WRITE OPERATION EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.5 PROTECTION STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6 FLASH IN-SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 ST92F124/F150/F250 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.7 STANDARD INTERRUPTS (CAN AND SCI-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.8 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.9 DEDICATED ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . 109
6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2 DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3 DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.9.8 118
6.4 DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.5 SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20
2/398
9




PDF 파일 내의 페이지 : 총 30 페이지

제조업체: ST Microelectronics

( stm )

ST92F150 data

데이터시트 다운로드
:

[ ST92F150.PDF ]

[ ST92F150 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


ST92F150

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM / E3 TMEMULATED EEPROM / CAN 2.0B AND J1850 BLPD - ST Microelectronics



ST92F150CR1

8/16-bit single voltage Flash MCU - STMicroelectronics



ST92F150CR9

8/16-bit single voltage Flash MCU - STMicroelectronics



ST92F150CV1

8/16-bit single voltage Flash MCU - STMicroelectronics



ST92F150CV9

8/16-bit single voltage Flash MCU - STMicroelectronics



ST92F150JDV1

8/16-bit single voltage Flash MCU - STMicroelectronics