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PDF ST24E64 Data sheet ( Hoja de datos )
| Número de pieza | ST24E64 | |
| Descripción | (ST24E64 / ST25E64) SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM | |
| Fabricantes | ST Microelectronics | |
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ST24E64
ST25E64
SERIAL EXTENDED ADDRESSING COMPATIBLE
WITH I2C BUS 64K (8K x 8) EEPROM
COMPATIBLE with I2C EXTENDED
ADDRESSING
TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES, OVER
the FULL SUPPLY VOLTAGE RANGE
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E64 version
– 2.5V to 5.5V for ST25E64 version
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
PRELIMINARY DATA
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
200mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST24/25E64 are 64K bit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 1024 x 8 bits. The ST25E64 operates
with a power supply value as low as 2.5V. Both
Plastic Dual-in-Line and Plastic Small Outline pack-
ages are available.
Table 1. Signal Names
E0 - E2
SDA
SCL
WC
VCC
VSS
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
Write Control
Supply Voltage
Ground
VCC
3
E0-E2
SCL
WC
ST24E64
ST25E64
SDA
VSS
AI01204B
November 1996
This is preliminary information on a new product now in development or undergoing evaluatio n.Details are subject to change without notice.
1/16
1 page  
ST24E64, ST25E64
Table 5. Input Parameters (1) (TA = 25 °C, f = 400 kHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN Input Capacitance (SDA)
CIN Input Capacitance (other pins)
ZWCL
WC Input Impedance
ZWCH
WC Input Impedance
tLP
Low-pass filter input time constant
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.
VIN ≤ 0.3 VCC
VIN ≥ 0.7 VCC
8
6
5 20
500
100
pF
pF
kΩ
kΩ
ns
Table 6. DC Characteristics
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
(SCL, SDA, E0-E2)
0V ≤ VIN ≤ VCC
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
SDA in Hi-Z
Supply Current (ST24 series)
ICC
Supply Current (ST25 series)
fC = 400kHz
(Rise/Fall time < 30ns)
ICC1
Supply Current (Standby)
(ST24 series)
VIN = VSS or VCC,
VCC = 5V
VIN = VSS or VCC,
VCC = 5V, fC = 400kHz
ICC2
Supply Current (Standby)
(ST25 series)
VIL Input Low Voltage (SCL, SDA)
VIH Input High Voltage (SCL, SDA)
VIN = VSS or VCC,
VCC = 2.5V
VIN = VSS or VCC,
VCC = 2.5V, fC = 400kHz
VIL Input Low Voltage (E0-E2, WC)
VIH Input High Voltage (E0-E2, WC)
Output Low Voltage
VOL
IOL = 3mA, VCC = 5V
Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V
Min Max
±2
±2
2
1
100
300
5
50
–0.3
0.7 VCC
–0.3
VCC – 0.5
0.3 VCC
VCC + 1
0.5
VCC + 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
5/16
5 Page 
Figure 9. Write Modes Sequence with Write Control = 1
ST24E64, ST25E64
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
WC (cont’d)
PAGE WRITE
(cont’d)
NO ACK
NO ACK
DATA IN N
AI01120
sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25E64 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E64terminate
the data transfer and switch to a standby state.
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ST24E64.PDF ] | |
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