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PDF UDA1334TS Data sheet ( Hoja de datos )
| Número de pieza | UDA1334TS | |
| Descripción | Low power audio DAC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1334TS
Low power audio DAC
Preliminary specification
File under Integrated Circuits, IC01
1999 Nov 11
1 page  
Philips Semiconductors
Low power audio DAC
Preliminary specification
UDA1334TS
SYMBOL
PARAMETER
CONDITIONS
Power dissipation (at fs = 44.1 kHz)
P power dissipation
play-back mode; at 2.0 V
supply voltage
play-back mode; at 3.0 V
supply voltage
Sleep mode
Note
1. The DAC output voltage scales proportional to the power supply voltage.
MIN. TYP. MAX. UNIT
− 7.0 − mW
− 17 − mW
− 0.5 − mW
6 BLOCK DIAGRAM
handbook, full pagewidth
BCK
WS
DATAI
1
2
3
VDDD
4
SYSCLK
MUTE
DEEM
PCS
UDA1334TS
6
8
9
10
VSSD
5
DIGITAL INTERFACE
DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
7 SFOR1
11 SFOR0
14
VOUTL
13
VDDA
DAC
DAC
15
VSSA
16
VOUTR
12
Vref(DAC)
MGL877
1999 Nov 11
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
Low power audio DAC
Preliminary specification
UDA1334TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pins; note 2
VIH HIGH-level input voltage
VIL LOW-level input voltage
ILI input leakage current
Ci input capacitance
3-level input: pin PCS
VIH HIGH-level input voltage
VIM MID-level input voltage
VIL LOW-level input voltage
DAC
at 2.0 V supply voltage
at 3.0 V supply voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
1.3 −
2.0 −
−0.5 −
−0.5 −
−−
−−
0.9VDDD
0.4VDDD
0
−
−
−
3.3 V
5.0 V
+0.5 V
+0.8 V
1 µA
10 pF
VDDD
0.6VDDD
0.5
V
V
V
Vref(DAC)
RO(ref)
reference voltage
Vref(DAC) reference output
resistance
with respect to VSSA
0.45VDD 0.5VDD
− 12.5
0.55VDD V
− kΩ
Io(max)
RL
CL
maximum output current
load resistance
load capacitance
(THD + N)/S < 0.1%;
RL = 800 Ω
note 3
−
3
−
tbf −
mA
− − kΩ
− 50 pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
14 AC CHARACTERISTICS
14.1 2.0 V supply voltage
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ. All voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
DAC
Vo(rms)
output voltage (RMS value)
∆Vo unbalance between channels
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
at 0 dB (FS) digital input
−
−
fs = 44.1 kHz; at 0 dB
fs = 44.1 kHz; at −60 dB;
A-weighted
−
−
fs = 96 kHz; at 0 dB
−
fs = 96 kHz; at −60 dB; A-weighted −
0.5 −
0.1 −
−80 −
−37 −
−75 −
−35 −
V
dB
dB
dB
dB
dB
1999 Nov 11
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UDA1334TS.PDF ] | |
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