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PDF UDA1335H Data sheet ( Hoja de datos )
| Número de pieza | UDA1335H | |
| Descripción | Universal Serial Bus USB Audio Playback Recording Peripheral APRP | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1335H
Universal Serial Bus (USB) Audio
Playback Recording Peripheral
(APRP)
Preliminary specification
File under Integrated Circuits, IC01
1998 Aug 28
1 page  
Philips Semiconductors
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
BLOCK DIAGRAM
Preliminary specification
UDA1335H
handbook, full pagewidth
VSSX
XTAL1b
XTAL2b
VDDX
VDDA3
XTAL2a
XTAL1a
VSSA3
24
25
26
28
52
53
54
55
CLK
27
OSC
48 MHz
TIMING
OSC
ADC
ANALOG
PLL
D+ D−
86
ANALOG FRONT-END
USB-PROCESSOR
P0.7 to P0.0
7, 5, 3, 64,
62, 60, 58, 56
P2.0 to P2.7
14, 16, 18, 20,
22, 23, 29, 30
9 VDDI
10 VSSI
11 VSSE
12 VDDE
32 VDDO
33 VSSO
38 VDDA1
39 VSSA1
42 VDDA2
44 VSSA2
GP2/DO 63
GP3/WSO 1
GP4/BCKO 2
GP1/DI 13
GP0/BCKI 17
GP5/WSI 15
PSEN 31
DA
WS
BCK
57
59
61
EA 48
ALE 50
VINL 43
VINR 47
VRN 49
VRP 51
PGA
PGA
DIGITAL I/O
MUX
I2S-BUS
INTERFACE
DECIMATOR
FILTER
SAMPLE
FREQUENCY
GENERATOR
FIFO
AUDIO FEATURE
PROCESSING DSP
UPSAMPLE FILTERS
LEFT
Σ∆ ADC
RIGHT
Σ∆ ADC
VARIABLE HOLD REGISTER
UDA1335H
3rd-ORDER NOISE SHAPER
LEFT
DAC
REFERENCE VOLTAGE
RIGHT
DAC
45, 46
n.c.
41
Vref(AD)
40
Vref(DA)
MICRO-
CONTROLLER
19 SCL
21 SDA
TEST
CONTROL
BLOCK
4 SHTCB
35 TC
36 RTCB
− 34 VOUTL
+
+ 37 VOUTR
−
MBK838
1998 Aug 28
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
Preliminary specification
UDA1335H
Table 3 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source
(analog input topology 1), see note 1.
APLL CLOCK
FREQUENCY (MHz)
8.1920
11.2896
12.2880
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
1 4.096
32
2 2.048
16
4 1.024
8
8
0.512 (not supported)
4 (not supported)
1 5.6448
44.1
2 2.8224
22.05
4 1.4112
11.025
8 0.7056
5.5125
1 6.144
48
2 3.072
24
4 1.536
12
8 0.768
6
Note
1. By using the APLL as a clock source 12 sample frequencies will be reported to the USB host.
Table 4 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source
(analog input topology 4), see note 1
OSCAD CLOCK
FREQUENCY (MHz)
fosc(2)
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
Q(3) fosc/(2Q)
fosc/(256Q)(4)
Notes
1. By using the OSCAD as a clock source, the sample frequency and the Q dividing factor must be filled in the
configuration map. Only this one sample frequency will be reported to the USB host.
2. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.
3. The Q factor can be 1, 2, 4 or 8.
4. Sample frequencies below 5 kHz and above 55 kHz are not supported.
1998 Aug 28
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UDA1335H.PDF ] | |
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