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PDF MTV018 Data sheet ( Hoja de datos )
| Número de pieza | MTV018 | |
| Descripción | Super On-Screen-Display | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTV018
FEATURES
Super On-Screen-Display
GENERAL DESCRIPTION
• Horizontal sync input may be up to 120 KHz.
• On-chip PLL circuitry up to 96 MHz.
• Programmable horizontal resolutions up to 1524 dots per dis-
play row.
• 942 bytes display registers to control full screen display.
• Full screen display consists of 15 (rows) by 30 (columns) char-
acters.
• 12 x 18 dot matrix per character.
• Total 256 characters and graphic fonts including 248 mask
ROM fonts and 8 programmable RAM fonts.
• 8 color selectable maximum per display character.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Bordering, shadowing and blinking effect.
• Programmable vertical character height (18 to 71 lines) control.
• Row to row spacing register to manipulate the constant display
height.
• 4 programmable background windows with multi-level operation
• Software clears for display frame.
• Polarity selectable to Hsync and Vsync inputs.
• Auto detection for input edge bounce distortion between Hsync
and Vsync inputs.
• Half tone and fast blanking output.
• Software force blank function for external display.
• 8 channels 8 bits PWM D/A converters output.
• Provide a clock output synchronous to the incoming Hsync for
external PWM D/A.
• Compatible to SPI bus or I2C interface.
• I2C interface with address 7AH (Slave address is mask option).
• 16 pins, 20 pins or 24 pins PDIP package.
MTV018 is designed for monitor applications to dis-
play the built-in characters or fonts onto monitor
screen. The display operation is by transferring data
and control information from micro controller to RAM
through a serial data interface. It can execute full
screen display automatically and specific functions
such as character bordering, shadowing, blinking,
double height and width, font by font color control,
frame positioning, frame size control by character
height and horizontal display resolution, and window-
ing effect. Moreover, MTV018 also provide 8 PWM
DAC channels with 8 bits resolution and a PWM
clock output for external digital to analog control.
BLOCK DIAGRAM
SSB
SCK
SDA
VFLB
HFLB
RP
VCO
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP
CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
PHASE LOCK LOOP VCLKX
PWM D/A
CONVERTER
8 DATA
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM
USER FONT RAM
LUMINANCE &
BORDGER
GENERATOR
LUMA
BORDER
DATA8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOUR
ENCODER
POWER ON
RESET
PRB
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.
1/16 MTV018 Revision 4.0 10/21/1999
1 page  
MYSON
TECHNOLOGY
MTV018
TABLE 1. The configuration of transmission formats.
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Address Bytes
of Display Reg.
Attribute Bytes
of Display Reg.
User Fonts
RAM
Row
Columnab
Columnc
Row
Columnab
Columnc
Row
Columnab
Columnc
1
0
0
1
0
0
1
0
0
0 0 x R3 R2 R1 R0 a,b,c
0 x C4 C3 C2 C1 C0 a,b
1 x C4 C3 C2 C1 C0
c
0 1 x R3 R2 R1 R0 a,b,c
0 x C4 C3 C2 C1 C0 a,b
1 x C4 C3 C2 C1 C0
c
1 x x x R2 R1 R0 a,b,c
0 C5 C4 C3 C2 C1 C0 a,b
1 C5 C4 C3 C2 C1 C0
c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure 3 on page 5.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X ROW
format (c) 0, 1
COLc
0, 1
format (b)
0, 0
COLab
1, X
X, X DAc
DAab
FIGURE 3. Transmission state diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
5/16 MTV018 Revision 4.0 10/21/1999
5 Page 
MYSON
TECHNOLOGY
MTV018
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the dis-
playing of characters or windows, otherwise, it outputs only during the displaying of characters.
B7 b6
b5
b4 b3
Column 18 TEST FBKGP PWMCK SELVCL HSP
b2 b1 b0
VSP VCO1 VCO0
TEST - = 0
=1
⇒ Normal mode.
⇒ Test mode, not allowed in applications.
FBKGP - Select the polarity of the output pin FBKG
= 1 ⇒Positive polarity FBKG output is selected.
= 0 ⇒Negative polarity FBKG output is selected.
The initial value is 1 after power up.
PWMCK - Select the output options to HTONE/PWMCK pin.
= 0 ⇒ HTONE option is selected.
= 1 ⇒ PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB.
The frequency is selected by (VCO1, VCO0) shown as Table 4 on page 12.
The initial value is 0 after power up.
SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition while the bit is set to
"1". The initial value is 0 after power up.
HSP - = 1 ⇒ Accept positive polarity Hsync input.
= 0 ⇒ Accept negative polarity Hsync input.
VSP -
= 1 ⇒ Accept positive polarity Vsync input.
= 0 ⇒ Accept negative polarity Vsync input.
VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and
horizontal resolution register (HORR).
(i) 12K ohm:
= (0, 0) ⇒ 6MHz < Pixel rate < 12MHz
= (0, 1) ⇒ 12MHz < Pixel rate < 24MHz
= (1, 0) ⇒ 24MHz < Pixel rate < 48MHz
= (1, 1) ⇒ 48MHz < Pixel rate < 96MHz
(ii) 11K ohm:
= (0, 0) ⇒ 6.5MHz < Pixel rate < 13MHz
= (0, 1) ⇒ 13MHz < Pixel rate < 26MHz
= (1, 0) ⇒ 26MHz < Pixel rate < 52MHz
= (1, 1) ⇒ 52MHz < Pixel rate < 96MHz
(iii)10K ohm:
= (0, 0) ⇒ 7MHz < Pixel rate < 14MHz
= (0, 1) ⇒ 14MHz < Pixel rate < 28MHz
= (1, 0) ⇒ 28MHz < Pixel rate < 56MHz
= (1, 1) ⇒ 56MHz < Pixel rate < 96MHz
(iv)9.1K ohm:
= (0, 0) ⇒ 7.5MHz < Pixel rate < 15MHz
= (0, 1) ⇒ 15MHz < Pixel rate < 30MHz
= (1, 0) ⇒ 30MHz < Pixel rate < 60MHz
= (1, 1) ⇒ 60MHz < Pixel rate < 96MHz
(v)8.2K ohm:
= (0, 0) ⇒ 8MHz < Pixel rate < 16MHz
= (0, 1) ⇒ 16MHz < Pixel rate < 32MHz
11/16
MTV018 Revision 4.0 10/21/1999
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MTV018.PDF ] | |
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