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ETC |
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
GENERAL DESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 1 0 15
32 14
33 ( T o p V i e w )
34
13
12
35 11
36 10
VCC
NC
nFOUT
FOUT
GND
NC
NC
VCC
GND
FEATURES
◆ Ideal for OC-12/48 data clock
◆ Integrated SAW delay line
◆ Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
◆ LVPECL clock output
◆ Pin-selectable feedback and reference divider ratios,
no programming required
◆ Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1010-01-155.5200
Frequency
Input (Mfin)
Ratio
Input Reference
Clock
(MHz)
Output
Clock MHz
8 19.44
2
77.76
155.52
1 155.52
Table 1: Example I/O Clock Frequency Combinations
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
M1010
0
1
R Div
Loop
Filter
M Div
Mfin Div
VCSO
3
SEL2:0
2
FIN_SEL1:0
Divider LUT
Mfin Divider
LUT
FOUT
nFOUT
Figure 2: Simplified Block Diagram
M1010-01 Datasheet Rev 0.4
Revised 29Sep2003
M1010-01 VCSO Based Clock Jitter Attenuator
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
DETAILED BLOCK DIAGRAM
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
M1010
MUX
0
1
REF_SEL
R Div
RLOOP CLOOP
RLOOP CLOOP
RPOST
RPOST
CPOST
CPOST
OP_IN nOP_IN OP_OUT nOP_OUT nVC VC
Phase
Detector
RIN
RIN Loop Filter
Amplifier
Phase
Locked
Loop
(PLL)
M Div
Mfin Divider
External
Loop Filter
Components
SAW Delay Line
Phase
Shifter
VCSO
3
SEL2:0
2
FIN_SEL1:0
Divider LUT
Mfin Divider
LUT
FOUT
nFOUT
PIN DESCRIPTIONS
Figure 3: Detailed Block Diagram
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
External loop filter connections.
See Figure 4, External Loop Filter, on pg. 4.
11, 18, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12, 13, 17, 25, 32
15
16
20
21
NC
FOUT
nFOUT
nDIF_REF1
DIF_REF1
No internal connection.
Output No internal terminator Clock output pairs. Differential LVPECL.
Input
Internal pull-UP resistor1 Reference clock input pair.
Internal pull-down resistor1 Differential LVPECL or LVDS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Internal pull-UP resistor1 Reference clock input pair.
Internal pull-down resistor1 Differential LVPECL or LVDS.
27
28
FIN_SEL1
FIN_SEL0
Input clock frequency selection. LVCMOS/LVTTL.
Input Internal pull-down resistor1 See Table 3, Mfin (Frequency Input) Divider Look-Up Table
(LUT) on pg. 3.
29
30
31
SEL0
SEL1
SEL2
Input
Internal pull-UP resistor1
M and R divider value selection. LVCMOS/ LVTTL.
See Table 4, SEL2:0 Look-up Table (LUT) on pg. 3.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see “Inputs with Pull-down” and “Inputs with Pull-up”
in Table 8, DC Characteristics, on pg. 6.
M1010-01 Datasheet Rev 0.4
2 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
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