파트넘버.co.kr 74HC4066N 데이터시트 PDF


74HC4066N 반도체 회로 부품 판매점

(74HC4066x) Quad bilateral switches



NXP Semiconductors 로고
NXP Semiconductors
74HC4066N 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74HC4066; 74HCT4066
Quad bilateral switches
Product specification
Supersedes data of 2003 Jun 17
2004 Nov 11


74HC4066N 데이터시트, 핀배열, 회로
Philips Semiconductors
Quad bilateral switches
Product specification
74HC4066; 74HCT4066
FEATURES
Very low ON-resistance:
– 50 (typical) at VCC = 4.5 V
– 45 (typical) at VCC = 6.0 V
– 35 (typical) at VCC = 9.0 V.
Complies with JEDEC standard no. 7A
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 °C to +85 °C and 40 °C to +125 °C.
GENERAL DESCRIPTION
The 74HC4066 and 74HCT4066 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4066B. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4066 and 74HCT4066 have four independent
analog switches. Each switch has two input/output pins
(pins nY or nZ) and an active HIGH enable input pin
(pin nE). When pin nE = LOW the belonging analog switch
is turned off.
The 74HC4066 and 74HCT4066 are pin compatible with
the 74HC4016 and 74HCT4016 but exhibit a much lower
on-resistance. In addition, the on-resistance is relatively
constant over the full input signal range.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
SYMBOL
PARAMETER
tPZH/tPZL
tPHZ/tPLZ
CI
CPD
CS
turn-on time nE to Vos
turn-off time nE to Vos
input capacitance
power dissipation
capacitance per switch
maximum switch
capacitance
CONDITIONS
TYPICAL
UNIT
74HC4066 74HCT4066
CL = 15 pF; RL = 1 k; VCC = 5 V 11 12 ns
CL = 15 pF; RL = 1 k; VCC = 5 V 13 16 ns
3.5 3.5 pF
notes 1 and 2
11 12 pF
8 8 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ[(CL + CS) × VCC2 × fo] = sum of the outputs.
2. For 74HC4066 the condition is VI = GND to VCC.
For 74HCT4066 the condition is VI = GND to VCC 1.5 V.
2004 Nov 11
2




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