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PDF MTV20N50E Data sheet ( Hoja de datos )
| Número de pieza | MTV20N50E | |
| Descripción | TMOS POWER FET 20 AMPERES 500 VOLTS RDS(on) = 0.240 OHM | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTV20N50E/D
™Designer's Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
D3PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage–blocking capability without degrading
performance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a drain–to–
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both ac–dc and dc–dc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
D
N–Channel
G
®
• Robust High Voltage Termination
• Avalanche Energy Specified
S
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured – Not Sheared
• Specifically Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm, 13–inch/500 Unit Tape & Reel, Add –RL Suffix to Part Number
MTV20N50E
TMOS POWER FET
20 AMPERES
500 VOLTS
RDS(on) = 0.240 OHM
CASE 433–01, Style 2
D3PAK Surface Mount
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
VDGR
VGS
500
500
±20
±40
Vdc
Vdc
Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 20 Adc
ID 14.1
IDM 60 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
PD 250 Watts
2.0 W/°C
3.57 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 10 mH, RG = 25 Ω )
EAS
2000
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC 0.5 °C/W
RθJA
62.5
RθJA
35
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
10
8
Q1
6
QT
Q2
VGS
500
400
300
4 200
ID = 20 A
TJ = 25°C
2 100
Q3 VDS
00
0 10 20 30 40 50 60 70 80 90 100
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
VDD = 250 V
ID = 20 A
VGS = 10 V
TJ = 25°C
100
MTV20N50E
td(off)
tr
tf
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
7
IS = 20 A
6 dlS/dt = 100 A/µs
VDD = 50 V
5 TJ = 25°C
4
20
TJ = 25°C
VGS = 0 V
16
12
38
2
4
1
0
0 2 4 6 8 10 12 14 16 18 20
ID, DRAIN CURRENT (AMPS)
Figure 10. Stored Charge
0
0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 0.86 0.9 0.94
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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