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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTY100N10E/D
™Designer's Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
MTY100N10E
Motorola Preferred Device
TMOS POWER FET
100 AMPERES
100 VOLTS
RDS(on) = 0.011 OHM
®
D
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 Ω )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
CASE 340G–02, STYLE 1
TO–264
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
EAS
Value
100
100
± 20
± 40
100
300
300
2.38
– 55 to 150
250
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
RθJC
RθJA
TL
0.42 °C/W
40
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© MMoototroorlao,lIancT. 1M99O5S Power MOSFET Transistor Device Data
1
MTY100N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 250 µA)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V(BR)DSS
100
—
—
115
— Vdc
— mV/°C
IDSS
µAdc
— — 10
— — 200
IGSS
— — 100 nAdc
VGS(th)
2.0 —
—7
4 Vdc
— mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 50 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 100 Adc)
(ID = 50 Adc, TJ = 125°C)
Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 50 Vdc, ID = 100 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 100 Adc, VGS = 0 Vdc)
(IS = 100 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
—
—
0.011
Ohm
Vdc
— 1.0 1.2
— — 1.0
30 49 — mhos
—
7600 10640
pF
—
3300
4620
—
1200
2400
— 48 96 ns
— 490 980
— 186 372
— 384 768
— 270 378 nC
— 50 —
— 150 —
— 118 —
Vdc
— 1 1.2
— 0.9 —
Reverse Recovery Time
(See Figure 14)
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
trr
ta
tb
QRR
LD
— 145 —
— 90 —
— 55 —
— 2.34 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 13 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data
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