DataSheet.es    


PDF BC41B143A-ds-002Pd Data sheet ( Hoja de datos )

Número de pieza BC41B143A-ds-002Pd
Descripción Blue Core ROM CSP EDR
Fabricantes CSR　
Logotipo CSR Logotipo



Hay una vista previa y un enlace de descarga de BC41B143A-ds-002Pd (archivo pdf) en la parte inferior de esta página.


Total 70 Páginas

No Preview Available ! BC41B143A-ds-002Pd Hoja de datos, Descripción, Manual

Device Features
_äìÉ`çêÉ»QJolj=`pm=bao
! Fully Qualified Bluetooth v2.0 + EDR System
! Enhanced Data Rate (EDR) compliant with
v2.0 of specification for both 2Mbits/s and
3Mbits/s modulation modes
! Full-speed Bluetooth Operation with Full
Piconet Support
! Scatternet Support
! 1.8V core, 1.7 to 3.6V I/O Split Rails
! Ultra Low Power Consumption
! Excellent Compatibility with Cellular
Telephones
! Minimum External Components Required
! Integrated 1.8V Linear Regulator
! USB and UART Port to 3MBits/s
! Support for 802.11 Co-existence
! RoHS Compliant
Single Chip Bluetooth®
v2.0 + EDR System
Product Data Sheet for
BC41B143A
September 2005
General Description
_äìÉ`çêÉQJolj=`pm is a single-chip radio and
baseband IC for Bluetooth 2.4GHz systems
including EDR to 3Mbits/s.
With the on-chip CSR Bluetooth software stack it
provides a fully compliant Bluetooth system to
v2.0 + EDR of the specification for data and voice
communications.
Applications
! Cellular Handsets
! Personal Digital Assistants (PDAs)
! Digital cameras and other high-volume consumer
products
! Space critical applications
BlueCore4-ROM CSP is designed to reduce the number
RAM
SPI of external components required. This ensures that
production costs are minimised.
RF IN
RF OUT
2.4
GHz
Radio
ROM
The device incorporates auto-calibration and built-in
UART/USB
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
I/O firmware is fully compliant with the Bluetooth v2.0 + EDR
Specification (all mandatory and optional features).
Baseband
DSP
MCU
PIO
To improve the performance of both Bluetooth and
802.11b/g co-located systems a wide range of
co-existence features are available including a variety of
PCM hardware signalling: basic activity signalling and Intel
WCS activity and channel signalling.
XTAL
BlueCore4-ROM CSP System Architecture
BC41B143A-ds-002Pd
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 1 of 89

1 page




BC41B143A-ds-002Pd pdf
Contents
List of Figures
Figure 3.1: BlueCore4-ROM CSP Package ............................................................................................................ 9
Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package .................................................................. 38
Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42
Figure 10.1: Basic Data Rate and Enhanced Data Rate Packet Types ................................................................ 46
Figure 10.2: π/4 DQPSK Constellation Pattern ..................................................................................................... 47
Figure 10.3: 8DPSK Constellation Pattern ............................................................................................................ 48
Figure 11.1: Circuit RF_A and RF_B..................................................................................................................... 49
Figure 11.2: Internal Power Ramping.................................................................................................................... 50
Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 52
Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 53
Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 54
Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 55
Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 57
Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 58
Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 59
Figure 11.10: Break Signal.................................................................................................................................... 61
Figure 11.11: UART Bypass Architecture ............................................................................................................. 62
Figure 11.12: USB Connections for Self Powered Mode ...................................................................................... 64
Figure 11.13: USB Connections for Bus-Powered Mode ...................................................................................... 64
Figure 11.14: USB_DETACH and USB_WAKE_UP Signalling............................................................................. 65
Figure 11.15: Write Operation ............................................................................................................................... 67
Figure 11.16: Read Operation............................................................................................................................... 67
Figure 11.17: BlueCore4-ROM CSP as PCM Interface Master............................................................................. 68
Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave............................................................................... 69
Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 69
Figure 11.20: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 69
Figure 11.21: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 70
Figure 11.22: GCI Interface................................................................................................................................... 70
Figure 11.23: 16-Bit Slot Length and Sample Formats ......................................................................................... 71
Figure 11.24: PCM Master Timing Long Frame Sync ........................................................................................... 73
Figure 11.25: PCM Master Timing Short Frame Sync........................................................................................... 73
Figure 11.26: PCM Slave Timing Long Frame Sync ............................................................................................. 74
Figure 11.27: PCM Slave Timing Short Frame Sync............................................................................................. 75
Figure 11.28: Example EEPROM Connection ...................................................................................................... 78
Figure 11.29: Example TXCO Enable OR Function .............................................................................................. 78
Figure 12.1: Application Circuit for CSP Package ................................................................................................. 81
Figure 14.1: BlueCore4-ROM CSP Package Dimensions..................................................................................... 82
BC41B143A-ds-002Pd
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 5 of 89

5 Page





BC41B143A-ds-002Pd arduino
CSP Package Information
Test and Debug
RESETB
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
TEST_EN
Ball Pad Type
Description
E7
CMOS input with weak
internal pull-up
Reset if low. Input debounced so must be
low for >5ms to cause a reset
G6
CMOS input with weak
internal pull-up
Chip select for Serial Peripheral Interface
(SPI), active low
G5
CMOS input with weak
internal pull-down
SPI clock
F6
CMOS input with weak
internal pull-down
SPI data input into BlueCore
F7
CMOS output, tri-state with
weak internal pull-down
SPI data output from BlueCore
G7
CMOS input with strong
internal pull-down
For test purposes only (leave unconnected)
PIO Port
PIO[0]
PIO[1]
PIO[2]
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
AIO[0]
AIO[2]
Ball Pad Type
Bi-directional with
F3 programmable strength
internal pull-up/down
Bi-directional with
F4 programmable strength
internal pull-up/down
Bi-directional with
G1 programmable strength
internal pull-up/down
Bi-directional with
G2 programmable strength
internal pull-up/down
Bi-directional with
E6 programmable strength
internal pull-up/down
Bi-directional with
F5 programmable strength
internal pull-up/down
Bi-directional with
D7 programmable strength
internal pull-up/down
Bi-directional with
E5 programmable strength
internal pull-up/down
Bi-directional with
E3 programmable strength
internal pull-up/down
Bi-directional with
F1 programmable strength
internal pull-up/down
Bi-directional with
F2 programmable strength
internal pull-up/down
D3 Bi-directional
C3 Bi-directional
Description
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
BC41B143A-ds-002Pd
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 11 of 89

11 Page







PáginasTotal 70 Páginas
PDF Descargar[ Datasheet BC41B143A-ds-002Pd.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
BC41B143A-ds-002PdBlue Core ROM CSP EDRCSR
CSR

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar