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PDF MTB15N06E Data sheet ( Hoja de datos )
| Número de pieza | MTB15N06E | |
| Descripción | TMOS POWER FET 15 AMPERES | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB15N06E/D
™Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain–to–source diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
G
®
D
S
MTB15N06E
Motorola Preferred Device
TMOS POWER FET
15 AMPERES
RDS(on) = 0.12 OHM
60 VOLTS
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS 60 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR 60 Vdc
Gate–Source Voltage — Continuous
VGS
± 20 Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 15 Adc
ID 10
IDM 40 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD 75 Watts
0.6 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vpk, IL = 15 Apk, L = 0.98 mH, RG = 25 Ω )
EAS 110 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.67 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMoottoororolal,aInTc.M19O9S4 Power MOSFET Transistor Device Data
1
1 page  
1250
VGS = 0
TJ = 25°C
1000 VDS = 0
750
500 Ciss
250 Coss
Crss
0
20 10 0 10 20 30
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
VDD = 30 V
ID = 15 A
200 VGS = 10 V
TJ = 25°C
100
20
10
MTB15N06E
tr
tf
td(off)
td(on)
2
1
12
10 20
RG, GATE RESISTANCE (OHMS)
100
Figure 8. Resistive Switching Time
Variation versus Gate Resistance
1000
200
100 OPERATION LIMITED IN THIS
AREA BY RDS(on)
20
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 µs
100 µs
1 ms
2
1
0.2
0.1
0.1
THERMAL LIMIT
PACKAGE LIMIT
RDS(on) LIMIT
0.2 1 2 10 20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
10 ms
dc
100
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
110
100
90
80
70
60
50
40
30
20
10
0
25
PEAK IL = 15 A
VDD = 25 V
50 75 100 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 10. Maximum Avalanche Energy versus
Starting Junction Temperature
VDS
t RG
L
IL
VDD
Figure 11. Unclamped Inductive Switching
Test Circuit
BVDSS
IL(t)
VDD
tP t, (TIME)
Figure 12. Unclamped Inductive Switching Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MTB15N06E.PDF ] | |
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