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PDF DS1004 Data sheet ( Hoja de datos )
| Número de pieza | DS1004 | |
| Descripción | 5-Tap High Speed Silicon Delay Line | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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www.dalsemi.com
DS1004
5-Tap High Speed
Silicon Delay Line
FEATURES
All-silicon timing circuit
Five equally delayed clock phases per input
Precise tap-to-tap delay tolerances of ±0.5,
±0.75, or ±1 ns
Input-to-tap 1 delay of 5 ns
Delay tolerances of ±1.5 ns over temperature
and voltage
Leading and trailing edge precision preserves
the input symmetry
CMOS design with TTL compatibility
Standard 8-pin DIP and 150 mil 8-pin SOIC
Vapor phase, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
IN
TAP 2
TAP 4
GND
1
2
3
4
8 VCC
7 TAP 1
6 TAP 3
5 TAP 5
DS1004M 8-Pin DIP (300-mil)
See Mech. Drawings Section
IN
TAP 2
1
2
8 VCC
7 TAP 1
TAP 4
GND
3
4
6 TAP 3
5 TAP 5
DS1004Z 8-Pin SOIC (150-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-5 - TAP Output Number
VCC
GND
- +5 Volt Supply
- Ground
IN - Input
DESCRIPTION
The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a
standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a
standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge
accuracies and has the inherent reliability of an all-silicon delay line solution.
The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum input-
to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns. See
Table 1 for details. Tolerance over temperature and voltage is ±1.5 ns. Nominal tap-to-tap tolerances
range from ±0.5 ns to ±1.0 ns. Each output is capable of driving up to 10 LS loads.
For customers needing non-standard delay values, the Late Package Program (LPP) is available.
Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.
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1 page  
NOTES:
1. All voltages are referenced to ground.
DS1004
2. VCC=5 volts and 25°C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (VCC):
Input Pulse:
25°C ±=3°C
5.0V ±=0.1V
High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance:
Rise and Fall Time:
50 ohm max.
3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width:
Pulse Period:
Output Load
Capacitance:
500 ns
1 µs
15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
5 of 6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DS1004.PDF ] | |
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