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PDF K5D5657ACM-F015 Data sheet ( Hoja de datos )
| Número de pieza | K5D5657ACM-F015 | |
| Descripción | MCP / 256Mb NAND and 256Mb Mobile SDRAM | |
| Fabricantes | Samsung Electronics | |
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K5D5657ACM-F015
PrelAimdvinanacrye
MCP MEMORY
MCP Specification of
256Mb NAND and 256Mb Mobile SDRAM
- 1 - Revision 0.1
September 2003
1 page  
K5D5657ACM-F015
PIN DESCRIPTION
Pin Name
CLK
CKE
/CS
/RAS
/CAS
/WEd
A0 ~ A12
BA0 ~ BA1
LDQM
UDQM
DQ0d ~ DQ15d
Vdd
Vddq
Vss
Vssq
Pin Function(Mobile SDRAM)
System Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Address Input
Lower Input/Output Data Mask
Upper Input/Output Data Mask
Data Input/Output
Power Supply
Data Out Power
Ground
DQ Ground
PrelAimdvinanacrye
MCP MEMORY
Pin Name
/CE
/RE
/WP
/WE
ALE
CLE
R/B
IO0 ~ IO7
Vcc
Vccq
Vss
Pin Function(NAND Flash)
Chip Enable
Read Enable
Write Protection
Write Enable
Address Latch Enable
Command Latch Enable
Ready/Busy Output
Data Input/Output
Power Supply
Data Out Power
Ground
Pin Name
NC
DNU
Pin Function
No Connection
Do Not Use
ORDERING INFORMATION
K 5 D 56 57 A C M - F 0 15
Samsung
MCP Memory(2chips)
Device Type
NAND Flash + Mobile SDRAM
NAND Flash Density,
Organization
56 : 256Mbit, x8
Mobile SDRAM Density, Organization
57 : 256Mbit, x16
Mobile SDRAM Speed
15 = 15ns, CL=2
NAND Flash Speed
0 = None
Package
F = FBGA(Leaded)
Version
M= 1st Generation
Operating Voltage
A: 1.8V / 1.8V
Flash Block Architecture
C = Uniform Block
NOTE :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
- 5 - Revision 0.1
September 2003
5 Page 
K5D5657ACM-F015
PrelAimdvinanacrye
MCP MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
2013
Typ.
-
Max
2048
Unit
Blocks
NOTE :
1. This device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. The 2nd and 3rd blocks are good upon shipping.
4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
( Vcc=1.7V~1.95V , TA=-25 to 85°C unless otherwise noted)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (VccQ:1.8V +/-10%)
Value
0V to VccQ
5ns
VccQ/2
1 TTL GATE and CL=30pF
CAPACITANCE(TA=25°C, VCC=1.8V , f=1.0MHz)
Item
Symbol
Test Condition
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
MODE SELECTION
CLE ALE
CE
WE
RE GND
HLL
HX
LHL
HX
HLL
HX
LHL
HX
LLL
HL
L L LH
L
XXXXXL
XXXXXX
X X(1) X X X X
X X H X X 0V
NOTE :
1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP Mode
X Command Input
Read Mode
X Address Input(3clock)
H Command Input
Write Mode
H Address Input(3clock)
H Data Input
X Data Output
H During Program(Busy)
H During Erase(Busy)
L Write Protect
0V/VCC(2) Stand-by
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Program Time
tPROG
-
200 500
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
2
3
Block Erase Time
tBERS
-
2
3
Unit
pF
pF
Unit
µs
cycles
cycles
ms
- 11 -
Revision 0.1
September 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K5D5657ACM-F015.PDF ] | |
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