8417902xx 반도체 회로 부품 판매점
Microcircuit / Monolithic Silicon
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 Lansdale |
REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
A Add device types 03 and 04. Convert to standard military drawing format and
change drawing CAGE code. Add figure 4, test circuit and switching
waveforms. Inactivate device types 01 and 02 for new design. Editorial
changes throughout.
B Update to reflect latest changes in format and requirements. Editorial changes
throughout. --les
88-12-20
05-02-08
APPROVED
M. A. Frye
Raymond Monnin
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED.
CURRENT CAGE CODE 67268
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
REV
BBBBBBBBBBBBB
SHEET
1 2 3 4 5 6 7 8 9 10 11 12 13
PREPARED BY
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
Greg A. Pitz
CHECKED BY
Ray Monnin
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
85-05-08
REVISION LEVEL
B
DSCC FORM 2233
APR 97
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
MICROCIRCUITS, DIGITAL, TTL, OCTAL
D-TYPE TRANSPARENT LATCH,
MONOLITHIC SILICON
SIZE
A
SHEET
CAGE CODE
14933
1 OF 13
84179
5962-E139-05
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
84179
01
R
X
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type. The device type identify the circuit function as follows:
Device type
Generic number
Circuit function
01, 03
8282
Octal, D-type, transparent latch with 3-state outputs
02, 04
8283
Octal, D-type, transparent latch with inverted 3-state outputs
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
R
GDIP1-T20 or CDIP2-T20 20
dual-in-line
3
CQCC1-N28
28 leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range .......................................................
Input voltage range .......................................................
Storage temperature range..............................................
Maximum power dissipation (PD) 1/ ..............................
Lead temperature (soldering, 10 seconds) .....................
Thermal resistance, junction-to-case (θJC) .....................
Junction temperature (TJ) ................................................
1.4 Recommended operating conditions.
-0.5 V dc to +7.0 V dc
-1.0 V dc at -18 mA to +5.5 V dc
-65°C to +150°C
1W
+300°C
See MIL-STD-1835
+175°C
Supply voltage :
Device types 01 and 02 ............................................................
Device types 03 and 04 ............................................................
Minimum high level input voltage (VIH) .........................................
Maximum low level input voltage (VIL) ..........................................
Case operating temperature range (TC) ........................................
Input to STB setup time t(setup) ......................................................
Input to STB hold time t(hold) ..........................................................
input pulse width (tP) (Strobe) .......................................................
4.5 V dc minimum to 5.5 V dc maximum
4.75 V dc minimum to 5.25 V dc maximum
2.0 V dc
0.8 V dc
-55°C to +125°C
0 ns minimum
25 ns minimum
15 ns minimum
_________
1/ Maximum power dissipation is defined as VCC x ICC, and must withstand the added PD due to short-circuit test; e.g., IOS.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
B
84179
SHEET
2
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