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74HC85 반도체 회로 부품 판매점

4-bit magnitude comparator



Philips 로고
Philips
74HC85 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT85
4-bit magnitude comparator
Product specification
File under Integrated Circuits, IC06
December 1990


74HC85 데이터시트, 핀배열, 회로
Philips Semiconductors
4-bit magnitude comparator
Product specification
74HC/HCT85
FEATURES
Serial or parallel expansion without extra gating
Magnitude comparison of any binary words
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are
weighted (A0 to A3 and B0 to B3), where A3 and B3 are the
most significant bits.
The operation of the “85” is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.
For proper compare operation the expander inputs (IA>B,
IA=B and IA<B) to the least significant position must be
connected as follows: IA<B = IA>B = = LOW and
IA=B = HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs QA<B, QAand QA=B to the
corresponding inputs of the significant comparator.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
CI
CPD
propagation delay
An, Bn to QA>B, QA<B
An, Bn to QA=B
IA<B,, IA=B, IA>B to QA<B, QA>B
IA=B to QA=B
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC HCT
UNIT
20 22 ns
18 20 ns
15 15 ns
11 15 ns
3.5 3.5 pF
18 20 pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2




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