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PDF 74HC4059 Data sheet ( Hoja de datos )
| Número de pieza | 74HC4059 | |
| Descripción | Programmable divide-by-n counter | |
| Fabricantes | Philips | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74HC4059 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4059
Programmable divide-by-n counter
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
1 page  
Philips Semiconductors
Programmable divide-by-n counter
Product specification
74HC/HCT4059
PIN DESCRIPTION
PIN NO.
SYMBOL NAME AND FUNCTION
1 CP clock input (LOW-to-HIGH, edge-triggered)
2 LE latch enable (active HIGH)
3, 4, 5, 6, 22, 21, 20, 19, 18, 17, 16, 15, 10, 9, 8, 7 J1 to J16 programmable JAM inputs (BCD)
12
GND
ground (0 V)
14, 13, 11
23
Ka to Kc mode select inputs
Q divide-by-n output
24 VCC positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
5
5 Page 
Philips Semiconductors
Programmable divide-by-n counter
AC WAVEFORMS
Product specification
74HC/HCT4059
(1) HC: VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (CP) to output (Q) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC: VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the LE input to Q output propagation delay.
(1) HC: VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the Kb or Kc removal times, when the operating mode is switched from master preset
to any other mode.
1998 Jul 08
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 74HC4059.PDF ] | |
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