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74HC4046 반도체 회로 부품 판매점

Phase-Locked Loop



ON 로고
ON
74HC4046 데이터시트, 핀배열, 회로
MC74HC4046A
Phase-Locked Loop
High–Performance Silicon–Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase–locked loop contains three phase
comparators, a voltage–controlled oscillator (VCO) and unity gain
op–amp DEMOUT. The comparators have two common signal inputs,
COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self–bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1OUT and
maintains 90 degrees phase shift at the center frequency between
SIGIN and COMPIN signals (both at 50% duty cycle). Phase
comparator 2 (with leading–edge sensing logic) provides digital error
signals PC2OUT and PCPOUT and maintains a 0 degree phase shift
between SIGIN and COMPIN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCOOUT whose frequency is
determined by the voltage of input VCOIN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op–amp output DEMOUT with an external resistor is used where the
VCOIN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op–amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage–to–frequency conversion and motor speed control.
Output Drive Capability: 10 LSTTL Loads
Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN)
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Low Quiescent Current: 80 µA Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates
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16
1
16
1
PDIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
MC74HC4046AN
AWLYYWW
1
16
HC4046A
AWLYWW
1
16
16
1
16
1
TSSOP–16
DT SUFFIX
CASE 948F
HC40
46A
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
74HC4046B
AWLYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package Shipping
MC74HC4046AN
PDIP–16 2000 / Box
MC74HC4046AD
SOIC–16 48 / Rail
MC74HC4046ADR2
SOIC–16 2500 / Reel
MC74HC4046AF
SOIC–EIAJ See Note
MC74HC4046AFEL
SOIC–EIAJ SNeOe TNAoGte
1. For ordering information on the EIAJ verNsOionToAfGthe
SOIC packages, please contact your local ON
Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1
Publication Order Number:
MC74HC4046A/D


74HC4046 데이터시트, 핀배열, 회로
MC74HC4046A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
PC3OUT
VCC
Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) VSS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
PIN ASSIGNMENT
PCPout
PC1out
COMPin
VCOout
INH
C1A
C1B
GND
1
2
3
4
5
6
7
8
16 VCC
15 PC3out
14 SIGin
13 PC2out
12 R2
11 R1
10 DEMout
9 VCOin
MAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 25 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
± 50
750
500
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPlastic DIP and SOIC Package†
– 65 to + 150
260
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
DC Supply Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND) NON–VCO
3.0 6.0
2.0 6.0
V
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Pin 5)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
– 55
0
0
0
VCC
+ 125
1000
500
400
V
_C
ns
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