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74F521MSA 반도체 회로 부품 판매점

8-Bit Identity Comparator



Fairchild 로고
Fairchild
74F521MSA 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F521
8-Bit Identity Comparator
General Description
The 74F521 is an expandable 8-bit comparator. It com-
pares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The
expansion input IA=B also serves as an active LOW enable
input.
Features
s Compares two 8-bit words in 6.5 ns typ
s Expandable to any word length
s 20-pin package
Ordering Code:
Order Number Package Number
Package Description
74F521SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F521SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F521MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F521PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009545
www.fairchildsemi.com


74F521MSA 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
A0–A7
B0–B7
IA=B
OA=B
Word A Inputs
Word B Inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active LOW)
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
1.0/1.0 20 µA/0.6 mA
1.0/1.0 20 µA/0.6 mA
1.0/1.0 20 µA/0.6 mA
50/33.3 1 mA/20 mA
Truth Table
IA = B
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
Note 1: A0 = B0, A1 = B1, A2 = B2, etc.
H
Logic Diagram
Inputs
A, B
A = B (Note 1)
AB
A = B (Note 1)
AB
Output
OA = B
L
H
H
H
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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