74F401PC 반도체 회로 부품 판매점
CRC Generator/Checker
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 Fairchild |
www.DataSheet4U.com
April 1988
Revised August 1999
74F401
CRC Generator/Checker
General Description
The 74F401 Cycle Redundancy Check (CRC) Generator/
Checker provides an advanced tool for implementing the
most widely used error detection scheme in serial digital
data handling systems. A 3-bit control input selects one-of-
eight generator polynomials. The list of polynomials
includes CRC-16 and CRC-CCITT as well as their recipro-
cals (reverse polynomials). Automatic right justification is
incorporated for polynomials of degree less than 16. Sepa-
rate clear and preset inputs are provided for floppy disk
and other applications. The Error output indicates whether
or not a transmission error has occurred. Another control
input inhibits feedback during check word transmission.
The 74F401 is fully compatible with all TTL families.
Features
s Eight selectable polynomials
s Error indicator
s Separate preset and clear controls
s Automatic right justification
s Fully compatible with all TTL logic families
s 14-pin package
s 9401 equivalent
s Typical applications:
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Ordering Code:
Order Number Package Number
Package Description
74F401SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F401PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009534
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
S0–S2
D
CP
CWE
P
MR
Q
ER
Description
Polynomial Select Inputs
Data Input
Clock Input (Operates on HIGH-to-LOW Transition)
Check Word Enable Input
Preset (Active LOW) Input
Master Reset (Active HIGH) Input
Data Output
Error Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F401 is a 16-bit programmable device which oper-
ates on serial data streams and provides a means of
detecting transmission errors. Cyclic encoding and decod-
ing schemes for error detection are based on polynomial
manipulation in modulo arithmetic. For encoding, the data
stream (message polynomial) is divided by a selected poly-
nomial. This division results in a remainder which is
appended to the message as check bits. For error check-
ing, the bit stream containing both data and check bits is
divided by the same selected polynomial. If there are no
detectable errors, this division results in a zero remainder.
Although it is possible to choose many generating polyno-
mials of a given degree, standards exist that specify a
small number of useful polynomials. The 74F401 imple-
ments the polynomials listed in Table 1 by applying the
appropriate logic levels to the select pins S0, S1 and S2.
The 74F401 consists of a 16-bit register, a Read Only
Memory (ROM) and associated control circuitry as shown
in the block diagram. The polynomial control code pre-
sented at inputs S0, S1 and S2 is decoded by the ROM,
selecting the desired polynomial by establishing shift mode
operation on the register with Exclusive OR gates at appro-
priate inputs. To generate the check bits, the data stream is
entered via the Data inputs (D), using the HIGH-to-LOW
transition of the Clock input (CP). This data is gated with
the most significant output (Q) of the register, and controls
the Exclusive OR gates Figure 1. The Check Word Enable
(CWE) must be held HIGH while the data is being entered.
After the last data bit is entered, the CWE is brought LOW
and the check bits are shifted out of the register and
appended to the data bits using external gating Figure 2.
To check an incoming message for errors, both the data
and check bits are entered through the D input with the
CWE input held HIGH. The 74F401 is not in the data path,
but only monitors the message. The Error Output becomes
valid after the last check bit has been entered into the
74F401 by a HIGH-to-LOW transition of CP. If no detect-
able errors have occurred during the data transmission, the
resultant internal register bits are all LOW and the Error
Output (ER) is LOW. If a detectable error has occurred, ER
is HIGH.
A HIGH on the Master Reset input (MR) asynchronously
clears the register. A LOW on the Preset input (P) asyn-
chronously sets the entire register if the control code inputs
specify a 16-bit polynomial; in the case of 12- or 8-bit check
polynomials only the most significant 12 or 8 register bits
are set and the remaining bits are cleared.
Select Code
S2 S1 S0
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
TABLE 1.
Polynomial
X16 + X15 + X2 + 1
X16 + X14 + X + 1
X16 + X15 + X13 + X7 + X4 + X2 + X1 + 1
X12 + X11 + X3 + X2 + X + 1
X8 + X7 + X5 + X4 + X + 1
X8 + 1
X16 + X12 + X5 + 1
X16 + X11 + X4 + 1
Remarks
CRC-16
CRC-16 REVERSE
CRC-12
LRC-8
CRC-CCITT
CRC-CCITT REVERSE
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