74F381SJ 반도체 회로 부품 판매점
4-Bit Arithmetic Logic Unit
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 Fairchild |
May 1988
Revised August 1999
74F381
4-Bit Arithmetic Logic Unit
General Description
The 74F381 performs three arithmetic and three logic oper-
ations on two 4-bit words, A and B. Two additional select
input codes force the function outputs LOW or HIGH. Carry
propagate and generate outputs are provided for use with
the 74F182 carry lookahead generator for high-speed
expansion to longer word lengths. For ripple expansion,
refer to the 74F382 ALU data sheet.
Features
s Low input loading minimizes drive requirements
s Performs six arithmetic and logic functions
s Selectable LOW (clear) and HIGH (preset) functions
s Carry generate and propagate outputs for use with carry
lookahead generator
Ordering Code:
Order Number Package Number
Package Description
74F381SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F381SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F381PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009528
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
A0–A3
B0–B3
S0–S2
Cn
G
P
F0–F3
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Function Outputs
U.L.
HIGH/LOW
1.0/3.0
1.0/3.0
1.0/1.0
1.0/4.0
50/33.3
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−1.8 mA
20 µA/−1.8 mA
20 µA/−0.6 mA
20 µA/−2.4 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
Signals applied to the Select inputs S0–S2 determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the Cn input of the least significant package.
The Carry Generate (G) and Carry Propagate (P) outputs
supply input signals to the 74F182 carry lookahead gener-
ator for expansion to longer word length, as shown in Fig-
ure 2. Note that an 74F382 ALU is used for the most
significant package. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S0 S1 S2
Operation
L L L Clear
H L L B Minus A
L H L A Minus B
H H L A Plus B
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
L
L
H
H
H A⊕B
H A+B
H AB
H Preset
Path Segment
Toward
F
Output
Cn + 4, OVR
Ai or Bi to P
7.2 ns
7.2 ns
Pi to Cn + ('F182)
6.2 ns
6.2 ns
Cn to F
8.1 ns
—
Cn or Cn + 4, OVR
— 8.0 ns
Total Delay
21.5 ns
21.4 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
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관련 데이터시트
74F381SC
4-Bit Arithmetic Logic Unit - Fairchild
74F381SJ
4-Bit Arithmetic Logic Unit - Fairchild